Year: 2015

SV Constraint random value generation : Introduction

System Verilog supports three different approaches in verification as follows. 1. Directed Testing 2. Random Testing 3. Directed Random/Constrained Random Testing Directed testing is the traditional verification approach. In this case, a particular scenario is created for a known feature and set the expectation for the same. So, the features have been verified can be

System Verilog : Mailbox

Synchronization and communication mechanisms are essential in our design, to control the interactions between processes or with a reactive testbench. This can be easily handled in System Verilog using semaphores, mailboxes and named events. Mailboxes are a message-based process synchronization and communication mechanism provided in SV. It allows messages to be exchanged between processes. Conceptually,

Minimum Pulse Width Check

Minimum pulse width checks are done to ensure that width of the clock signal is wide enough for the cell’s internal operations to complete. i.e. to get a stable output you need to ensure that the clock signal at the clock pin of the flop is at least of a certain ‘minimum’ width. If you

SVA Basics: Bind

Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interface or a compilation unit scope. There are many ways binding can be done. Following section discusses these. Normal Bind Binding fifo to fifo_sva