Year: 2017

String Split in SV

In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV, we need to do it in a roundabout way by parsing all the characters by using getc method. Below example shows how to split a

System Verilog: Random Number System Functions

System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers. The $random verilog system function has only one random number generator shared between all threads, but each thread in simulation has its own random number generator for $urandom and $urandom_range. Separate random number generators for each thread helps to improve random stability

System Verilog : Rand & Randc

There are two type-modifier keywords available in system Verilog to declare class variable as random. Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed over their range. Variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared

Noise Margins

Noise margin is the amount of noise a circuit can withstand without compromising its operation. These values are defined so that optimization and analysis can ensure that the spurious signals are not causing any functional issues. The noise values are checked against the noise margins and if they are exceeding the margins provided, an error

System Verilog : Disable Fork & Wait Fork

To model concurrent and serial behavior, disable fork and wait fork will be used along with fork join constructs. These constructs allow one process to terminate or wait for the completion of other processes. If you want to model your verification environment in such a way that, it has to spawn concurrent processes which will

System Verilog : Fork Join

The fork-join construct enables the creation of concurrent processes from each of its parallel blocks. All the blocks get the same start time and the finish time is controlled by the type of join construct used. Formal syntax for a parallel block.

With fork-join -which is available in conventional Verilog – procedure can continue