String Split in SV
In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV,… Read more »
In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV,… Read more »
System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers. The $random verilog system function has only one random number generator shared between all threads, but each… Read more »
There are two type-modifier keywords available in system Verilog to declare class variable as random. Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed… Read more »
Noise margin is the amount of noise a circuit can withstand without compromising its operation. These values are defined so that optimization and analysis can ensure that the spurious signals… Read more »
To model concurrent and serial behavior, disable fork and wait fork will be used along with fork join constructs. These constructs allow one process to terminate or wait for the… Read more »
The fork-join construct enables the creation of concurrent processes from each of its parallel blocks. All the blocks get the same start time and the finish time is controlled by… Read more »