Utility awk – Basics
The awk is a utility developed by Aho, Weinberger and Kerninghan (AWK). It is a pattern scanning and processing language.By default it reads from standard input and writes to standard… Read more »
Sini has spent more than a dozen years in the semiconductor industry, focusing mostly on verification. She is an expert on Formal Verification and has written international papers and articles on related topics.
The awk is a utility developed by Aho, Weinberger and Kerninghan (AWK). It is a pattern scanning and processing language.By default it reads from standard input and writes to standard… Read more »
In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV,… Read more »
System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers. The $random verilog system function has only one random number generator shared between all threads, but each… Read more »
There are two type-modifier keywords available in system Verilog to declare class variable as random. Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed… Read more »
To model concurrent and serial behavior, disable fork and wait fork will be used along with fork join constructs. These constructs allow one process to terminate or wait for the… Read more »
The fork-join construct enables the creation of concurrent processes from each of its parallel blocks. All the blocks get the same start time and the finish time is controlled by… Read more »
System Verilog supports three different approaches in verification as follows. 1. Directed Testing 2. Random Testing 3. Directed Random/Constrained Random Testing Directed testing is the traditional verification approach. In this… Read more »
Synchronization and communication mechanisms are essential in our design, to control the interactions between processes or with a reactive testbench. This can be easily handled in System Verilog using semaphores,… Read more »
Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a… Read more »
Array reduction methods can be applied to any unpacked array. The “with” clause can be used to specify the item to be used in the reduction. sum() : returns the… Read more »