Verilog: Control Statements

By using control statements, you can decide the order in which statements are executed. Conditional statements If-else case Loops forever repeat while for if-else Conditional statements are used to decide which statement in a group …

Verilog: Operators

Operators are single-, double-, or triple-character sequences and are used in expressions.Following operators are available in Verilog HDL. Please note that not all operators are synthesizable. {} {{}} Concatenation + – * / ** Arithmetic …

Clock Jitter

In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock jitter is a characteristic of the clock source and the clock signal environment. …