Author Archives: Sini Mukundan

Sini is an expert on physical design flow and related methodologies. Outside work, she is an avid reader and generally loves being lazy.

Multi Cycle Paths

By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that some data is captured only after a specified number of clock cycles. Till then, the data at the capturing flop will not be used. Of course your circuit should be designed in such

STA – Setup and Hold Time Analysis

It is easy to get confused with the definitions of setup and hold violations. We are used to the definitions of setup and hold times for a single flipflop. The setup and hold violation checks done by STA tools are slightly different. PT aptly calls them max and min delay analysis. However, the other terminology

Clock Jitter

In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock jitter is a characteristic of the clock source and the clock signal environment. It can be defined as “deviation of a clock edge from its ideal location.” Clock jitter is typically caused by

Insertion Delay & set_clock_latency

Clock latency refers to the delay that is assumed to exist between the clock source and the flip-flop clock pin. This is typically used before layout, when clock is ideal. It is not the actual delay, but the delay specified by the user, to account for the clock network delay after implementation. There are two


There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means. The SDC manual states that set_clock_uncertainty Specifies the uncertainty or skew characteristics of a single clock or between two different clocks. The timing analyzer uses this information to determine the worst possible clock arrival times for each timing check.

Physical Design Flow V: Physical Verification

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis IV. Routing After routing, your layout is complete. Now a number of checks are performed to verify that the drawn layout works as intended. Physical verification Equivalence Checking Timing Analysis Equivalence check will compare the netlist we started out with (pre-layout/synthesis netlist) to the netlist

Physical Design Flow IV:Routing

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis After CTS, the routing process determines the precise paths for interconnections. This includes the standard cell and macro pins, the pins on the block boundary or pads at the chip boundary. After placement and CTS,the tool has information about the exact locations of blocks, pins

Physical Design Flow III:Clock Tree Synthesis

I. NetlistIn & Floorplan II. Placement For synchronized designs, data transfer between functional elements are synchronized by clock signals. In a top level digital design, you will have one more more clock sources, like PLLs or oscillators within the chip. You may also have an external clock source connection through an IO. For a digital

Physical Design Flow II:Placement

I. NetlistIn & Floorplan After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to let the tool to do standard cell placement. The tool determines the location of each of the components (in digital design, standard cell instantiations) on

Physical Design Flow I : NetlistIn & Floorplanning

This is going to be a series of step-by-step explanation of physical design flow for the novice. I am going to list out the stages from Netlist-GDS in this session. Of course some say synthesis should also be part of physical design, but we will skip that for now. So, you have completed your RTL,