Author Archives: Sini Mukundan

Sini is an expert on physical design flow and related methodologies. Outside work, she is an avid reader and generally loves being lazy.


set_timing_derate set_timing_derate is a command that lets you constraint the timing a bit more. The idea and application is simple enough, but you might get confused with all the talk about process variation and OCV whenever someone starts on derate. Best option is, forget the OCV. Let’s uncomplicate and first see how the command works.

Creating .lib file from verilog

Creating a dummy .lib file is something every physical design engineer has done now and then. If you have a verilog model of the block available, your task gets easier. The following script automates .lib generation from your verilog netlist. Use this as a dummy .lib to get your design flow going or use it


Engineering Change Order or ECO is how you incorporate last minute changes in your design. ECO saves money and time and is prevalent in the industry. When I talk ECO, I am talking about ECOs in the layout. So typically you start with an ECO on the gate level netlist. The designer need to edit

Spare Cells

I have been writing an article on ECO flows.Of course I cannot talk about freeze_silicon ECOs without talking about spare cells.When I was a wee intern sitting through PnR training, spare cells confused me. I thought I had to insert the spares and use them in the same session! So here’s a small note about

SPEF Files Explained

Standard Parasitic Exchange Format(SPEF) is an IEEE format for specifying chip parasitics. The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System . Latest version of SPEF is part of 1481-2009 IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA) . The SPEF

ICCompiler MCMM Flow – create_scenario

The PnR tools now have concurrent multi-corner and multimode analysis and optimization capabilities. In ICCompiler, we create scenarios to specify the different corners and modes the design should operate on. In a scenario, you can have constraints which determine the mode of operation, and different libraries(or opertaing conditions) which determine the corners. You also set

Reading ICC Timing Reports

At any stage of the design you will be reporting timing. You can use your PnR tool to report the timing after placement, after CTS and various stages of routing and optimization. Even though the P&R timing reports are not signoff STA, they are still very important in understanding the tool behaviour. ICCompiler & PT

Synopsys Design Constraints

Timing closure is the big whale for most P&R designers. You get it done, and then you can wash your hands off all those annoying designers and get to work cleaning up and beautifying your layout.