Back End
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5.6K2Useful Skew
For clock trees, the traditional way is to go with zero skew or balanced skew. For each of the sinks, the insertion...
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Physical Only Cells: Filler Cells
Let us continue with the physical only cells present in the standard cell libraries that ease the digital PD flow. Filler Cells...
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9.7K3Physical Only Cells; Well Taps & Decap Cells
In PD flow, you must have come across the term physical only cells. Let us explore a few of them. Well Tap...
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6.5K2CMOS Latchup
Latch-Up is a condition where a low impedance path is created between a supply pin and ground. To understand latch up we...
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5.5K2Clock Gating Checks
As we saw in the earlier article on ICG, a gated clock is when you use a logic gate to control or...
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7.0KNoise Margins
Noise margin is the amount of noise a circuit can withstand without compromising its operation. These values are defined so that optimization...
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Minimum Pulse Width Check
Minimum pulse width checks are done to ensure that width of the clock signal is wide enough for the cell’s internal operations...
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Recovery and Removal Checks
Recovery and removal analysis are done on asynchronous signals like resets. These specify the requirement of these signals with respect to clock.Recovery...
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14.2K17Integrated Clock Gating Cell
Clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal.Clock...
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Standard Delay Format
SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF...