Back End

Standard Delay Format

SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF...

Multi Cycle Paths

By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that...

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STA – Setup and Hold Time Analysis

It is easy to get confused with the definitions of setup and hold violations. We are used to the definitions of setup...

Clock Jitter

In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock...

Insertion Delay & set_clock_latency

Clock latency refers to the delay that is assumed to exist between the clock source and the flip-flop clock pin. This is...

set_clock_uncertainty

There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means. The SDC manual states that set_clock_uncertainty...

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Physical Design Flow V: Physical Verification

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis IV. Routing After routing, your layout is complete. Now a number of...

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Physical Design Flow IV:Routing

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis After CTS, the routing process determines the precise paths for interconnections. This...

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Physical Design Flow III:Clock Tree Synthesis

I. NetlistIn & Floorplan II. Placement For synchronized designs, data transfer between functional elements are synchronized by clock signals. In a top...