Latch-Up is a condition where a low impedance path is created between a supply pin and ground. To understand latch up we...
As we saw in the earlier article on ICG, a gated clock is when you use a logic gate to control or...
Noise margin is the amount of noise a circuit can withstand without compromising its operation. These values are defined so that optimization...
Minimum pulse width checks are done to ensure that width of the clock signal is wide enough for the cell’s internal operations...
Recovery and removal analysis are done on asynchronous signals like resets. These specify the requirement of these signals with respect to clock.Recovery...
Clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal.Clock...
SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF...
By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that...
It is easy to get confused with the definitions of setup and hold violations. We are used to the definitions of setup...
In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock...