Category Archives: Category: System Verilog

String Split in SV

In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV, we need to do it in a roundabout way by parsing all the characters by using getc method. Below example shows how to split a

System Verilog: Random Number System Functions

System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers. The $random verilog system function has only one random number generator shared between all threads, but each thread in simulation has its own random number generator for $urandom and $urandom_range. Separate random number generators for each thread helps to improve random stability

System Verilog : Rand & Randc

There are two type-modifier keywords available in system Verilog to declare class variable as random. Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed over their range. Variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared

System Verilog : Disable Fork & Wait Fork

To model concurrent and serial behavior, disable fork and wait fork will be used along with fork join constructs. These constructs allow one process to terminate or wait for the completion of other processes. If you want to model your verification environment in such a way that, it has to spawn concurrent processes which will

System Verilog : Fork Join

The fork-join construct enables the creation of concurrent processes from each of its parallel blocks. All the blocks get the same start time and the finish time is controlled by the type of join construct used. Formal syntax for a parallel block.

With fork-join -which is available in conventional Verilog – procedure can continue

SV Constraint random value generation : Introduction

System Verilog supports three different approaches in verification as follows. 1. Directed Testing 2. Random Testing 3. Directed Random/Constrained Random Testing Directed testing is the traditional verification approach. In this case, a particular scenario is created for a known feature and set the expectation for the same. So, the features have been verified can be

System Verilog : Mailbox

Synchronization and communication mechanisms are essential in our design, to control the interactions between processes or with a reactive testbench. This can be easily handled in System Verilog using semaphores, mailboxes and named events. Mailboxes are a message-based process synchronization and communication mechanism provided in SV. It allows messages to be exchanged between processes. Conceptually,

System Verilog : Array Reduction & Array Ordering Methods

Array reduction methods can be applied to any unpacked array. The “with” clause can be used to specify the item to be used in the reduction. sum() : returns the sum of all the array elements. product() : returns the product of all the array elements and() : returns the bit-wise AND(&) of all the

System Verilog : Array querying system functions

System Verilog provides some system functions to query about arrays. The return value of this system function is int and it can be applied to all arrays. Different array querying functions are $dimension : Returns the number of dimensions in the array and 1 for strings and simple bit vectors and 0 for any other

System Verilog : Queues

In your system verilog code, if extraction and insertion order of array elements are important, queue would be the best option. A queue is a variable-size, ordered collection of homogeneous elements. It is declared using the same syntax as unpacked arrays, but specifying $ as the array size. It is analogous to a one-dimensional unpacked