System Verilog: Associative Arrays
Associative array is one of aggregate data types available in system verilog. We have already discussed about dynamic array, which is useful for dealing with contiguous collection of variables whose… Read more »
Category: System Verilog
System Verilog: Dynamic Arrays
`Dynamic array` is one of the aggregate data types in system verilog. It is an unpacked array whose size can be set or changed at run time. In verilog, dimension… Read more »
SV Event Scheduling Algorithm
While simulating System Verilog design and its test-bench including assertions, events has to be dynamically scheduled, executed, and removed as the simulator advances time. To have this feature, simulator has… Read more »