Category Archives: Category: Verilog

String Split in SV

In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV, we need to do it in a roundabout way by parsing all the characters by using getc method. Below example shows how to split a

Verilog: Timescales

As we are aware, compiler directive `timescale in Verilog is a tricky topic and have many discussion around it. Timescale specifies the time unit and time precision of a module that follow it. The simulation time and delay values are measured using time unit. The precision factor is needed to measure the degree of accuracy

Verilog: Timing Controls

Timing Controls Timing control statements are required in simulation to advance time. The time at which procedural statements will get executed shall be specified using timing controls. Delay based, event based and level sensitive timing controls are available in Verilog. Each of these are discussed below. Delay Based Timing Control In this, timing control is

Verilog: Continuous & Procedural Assignments

Continuous Assignment Continuous assignment is used to drive a value on to a net in dataflow modeling. The net can be a vector or scalar, indexed part select, constant bit or part select of a vector. Concatenation is also supported with scalar vector types.

Regular & Implicit Assignment Regular continuous assignment means, the declaration

Verilog: Task & Function

Task and Function are used to break up large procedures into smaller ones which helps to make life easier for developing and maintaining Verilog code. In this way, common procedures need to be written only once and can execute from different places. Both task and function are called from always or initial block and contain

Verilog: Control Statements

By using control statements, you can decide the order in which statements are executed. Conditional statements If-else case Loops forever repeat while for if-else Conditional statements are used to decide which statement in a group of choices is executed. If a condition is evaluated to true, one statement is executed. If the condition evaluated to

Verilog: Operators

Operators are single-, double-, or triple-character sequences and are used in expressions.Following operators are available in Verilog HDL. Please note that not all operators are synthesizable. {} {{}} Concatenation + – * / ** Arithmetic % Modulus > >= < Logical right shift > Arithmetic right shift ? : Conditional or Event or Concatenation Operators