Verilog: Timescales

As we are aware, compiler directive `timescale in Verilog is a tricky topic and have many discussion around it. Timescale specifies the time unit and time precision of a module that follow it. The simulation …

Verilog: Timing Controls

Timing Controls Timing control statements are required in simulation to advance time. The time at which procedural statements will get executed shall be specified using timing controls. Delay based, event based and level sensitive timing …

Verilog: Control Statements

By using control statements, you can decide the order in which statements are executed. Conditional statements If-else case Loops forever repeat while for if-else Conditional statements are used to decide which statement in a group …