## SVA Sequences IV : Methods

Method .triggered This is built-in method on a sequence . This is a method to break down the complex sequence to simpler sub-sequences. The endpoint of sub-sequence can be detected using the method triggered. When …

## SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence

Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators. Single delay concatenation operator (##1) zero-delay concatenation operator (##0) Single delay concatenation operator (##1)

Match of mult_seq1 …

## SV Event Scheduling Algorithm

While simulating System Verilog design and its test-bench including assertions, events has to be dynamically scheduled, executed, and removed as the simulator advances time. To have this feature, simulator has to maintain a data structure …

## SVA Sequences III – Other Operators

Operator AND The binary operator AND is used when both operands are expected to match, but the end times of the operand sequences may be different. That means, when one of the operand sequence match, …

## Hamming Code

In data transmission, error detection is required as there are high chances of having bit changes in the data. Hamming code is a linear error-detecting and correcting code invented by R. W. Hamming. It can …

## SVA Sequences II – Repetition Operators

There are three different kinds of repetition operators available in SVA viz., consecutive, non-consecutive and goto. For all three operators the number of iterations can be either specified by an exact count or by a …

## SVA Sequences I : Basics

Sequences Sequence is a finite list of System Verilog Boolean expressions which matches along a finite interval of consecutive clock ticks. It evaluates Boolean expressions to true in each clock tick till the last expression. …

## Code Coverage Fundamentals

Coverage is a metric to assess the progress of functional verification activity. This plays a major role to get a clear picture on how well the design has been verified and also to identify the …

## SVA : System Tasks & Functions

Assertion severity – system tasks In System Verilog, severity of assertion messages is classified by using four system tasks. These are \$fatal, \$error, \$warning and \$info. If an action block is specified, user-defined severity can …

## SVA : Concurrent Assertions

Concurrent Assertions Concurrent assertions are based on clock semantics and are evaluated continuously with every clock edge. Concurrent assertions can be temporal that means usually it describes a certain behavior that spans over a time …