Category Archives: Category: Front End

SVA Properties III : Implication

The implication construct (|->) allows a us to monitor sequences based on satisfying some criteria, i.e. for a sequence to occur, a preceding sequence must have occurred. The implication consists of left-hand-side called antecedent, an implication operator and right-hand-side called consequence. The implication is a construct located between antecedent and consequence and if there is

Verilog: Operators

Operators are single-, double-, or triple-character sequences and are used in expressions.Following operators are available in Verilog HDL. Please note that not all operators are synthesizable. {} {{}} Concatenation + – * / ** Arithmetic % Modulus > >= < Logical right shift > Arithmetic right shift ? : Conditional or Event or Concatenation Operators

SVA Properties II : Types

Sequence Properties Properties which contain sequence definitions are called sequence properties.Sequence properties are of three types. weak(sequence_expr) If there is no finite prefix that witnesses inability to match the sequence_expr, weak(sequence_expr) evaluates to true. The following example shows a weak sequential property p1.

An evaluation attempt of weak_assert assertion returns true in the following

SVA Properties I : Basics

Property defines set of behaviours of the design. To use those behaviors verification directive must be used. In other words, a property itself does not produce any result. A named property can be declared in module, interface, program, clocking block, package, compilation-unit scope, generate block or checker. In simulation run, property will be either in

Synchronous & Asynchronous Reset

Reset Reset is a signal that is used to initialize the hardware, as the design does not have a way to do self initialization. That means, reset forces the design to a known state. In simulation, usually it is activated at the beginning, but in real hardware, reset is usually activated to power up the

SVA Sequences IV : Methods

Method .triggered This is built-in method on a sequence . This is a method to break down the complex sequence to simpler sub-sequences. The endpoint of sub-sequence can be detected using the method triggered. When method triggered is evaluated in an expression, it tests whether its operand sequence has reached its end point at that

SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence

Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators. Single delay concatenation operator (##1) zero-delay concatenation operator (##0) Single delay concatenation operator (##1)

Match of mult_seq1 starts with a match of seq1 at posedge of clk1 and end with a match of seq2 at posedge clk2.

SV Event Scheduling Algorithm

While simulating System Verilog design and its test-bench including assertions, events has to be dynamically scheduled, executed, and removed as the simulator advances time. To have this feature, simulator has to maintain a data structure and usually would be a time ordered linked list. That means, at any point of time during simulation, event has

SVA Sequences III – Other Operators

Operator AND The binary operator AND is used when both operands are expected to match, but the end times of the operand sequences may be different. That means, when one of the operand sequence match, it waits for the other to match. Please note that both sequence must start at the same time.


Hamming Code

In data transmission, error detection is required as there are high chances of having bit changes in the data. Hamming code is a linear error-detecting and correcting code invented by R. W. Hamming. It can detect up to 2 bit errors (simultaneous) and can correct single bit error. The key concept in Hamming code calculation