Category Archives: Category: Front End

SVA Sequences II – Repetition Operators

There are three different kinds of repetition operators available in SVA viz., consecutive, non-consecutive and goto. For all three operators the number of iterations can be either specified by an exact count or by a finite range. If the number of repetitions is specified by an exact count [*n], then ‘n’ has to be a

SVA Sequences I : Basics

Sequences Sequence is a finite list of System Verilog Boolean expressions which matches along a finite interval of consecutive clock ticks. It evaluates Boolean expressions to true in each clock tick till the last expression. The major difference of sequence from a property is that, sequence does not have a success/fail status. Instead, it simply

Code Coverage Fundamentals

Coverage is a metric to assess the progress of functional verification activity. This plays a major role to get a clear picture on how well the design has been verified and also to identify the uncovered areas in verification. Code coverage and functional coverage are the two types of coverage methods used in functional verification.

SVA : System Tasks & Functions

Assertion severity – system tasks In System Verilog, severity of assertion messages is classified by using four system tasks. These are $fatal, $error, $warning and $info. If an action block is specified, user-defined severity can be created by using these system tasks. Every assertion failure has an associated severity which can be specified in the

SVA : Concurrent Assertions

Concurrent Assertions Concurrent assertions are based on clock semantics and are evaluated continuously with every clock edge. Concurrent assertions can be temporal that means usually it describes a certain behavior that spans over a time interval. The evaluation model for concurrent assertion is based on clock and the evaluation happens only at the occurrence of

SVA : Introduction

Introduction There is a popular statement about assertion, which says “an assertion is a statement that a given property is required to hold and a directive to verification tools to verify that it does hold”. In other words, an assertion specifies a behavior of the system and it is primarily used to validate the behavior

A glimpse on Metric Driven Verification Methodology

As the design complexity increases, the use of traditional verification methodology becomes minimal for verifying hardware designs. Directed Tests were used quite long back. Later, Coverage Driven Verification methodology (CDV) came up. In directed tests approach, verification engineer is going to state exactly what stimulus should be applied to the Design Under Test (DUT). This

Sequential Equivalence Checking for high performance design

Abstract: Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the déjà-vu situation of performance to time-to-market trade-offs; especially in high-performance designs. Sequential Equivalence Checking opens up possibilities in this area, by enabling performance-tuning related sequential micro-architectural changes to be verified with significantly lower impact on

Formal Verification – An Overview

Formal verification is a technique used in different stages in ASIC project life cycle like front end verification, Logic Synthesis, Post Routing Checks and also for ECOs. But when you go deep into it, the formal verification used for verifying RTLs is entirely different from others. There are different formal techniques available