String Split in SV
In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV,… Read more »
In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV,… Read more »
System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers. The $random verilog system function has only one random number generator shared between all threads, but each… Read more »
To model concurrent and serial behavior, disable fork and wait fork will be used along with fork join constructs. These constructs allow one process to terminate or wait for the… Read more »
The fork-join construct enables the creation of concurrent processes from each of its parallel blocks. All the blocks get the same start time and the finish time is controlled by… Read more »
Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a… Read more »
Once RTL is released, the next step is to go for synthesis to get a gate-level representation of the design. This is called synthesized netlist. Assumption is that synthesized netlist… Read more »
A property is called “until property” if it uses one of the below until operators. until s_until until_with s_until_with Until properties are categorized as Overlapped & Non-overlapped and Strong &… Read more »
The implication construct (|->) allows a us to monitor sequences based on satisfying some criteria, i.e. for a sequence to occur, a preceding sequence must have occurred. The implication consists… Read more »
Sequence Properties Properties which contain sequence definitions are called sequence properties.Sequence properties are of three types. weak(sequence_expr) If there is no finite prefix that witnesses inability to match the sequence_expr,… Read more »
Property defines set of behaviours of the design. To use those behaviors verification directive must be used. In other words, a property itself does not produce any result. A named… Read more »