SVA Basics: Bind
Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interface or a compilation …
Category: Assertion Based Verification
SVA Properties IV : Until Property
A property is called “until property” if it uses one of the below until operators. until s_until until_with s_until_with Until properties are categorized as Overlapped & Non-overlapped and Strong & Weak. So overall four different …
SVA Properties III : Implication
The implication construct (|->) allows a us to monitor sequences based on satisfying some criteria, i.e. for a sequence to occur, a preceding sequence must have occurred. The implication consists of left-hand-side called antecedent, an …
SVA Properties II : Types
Sequence Properties Properties which contain sequence definitions are called sequence properties.Sequence properties are of three types. weak(sequence_expr) If there is no finite prefix that witnesses inability to match the sequence_expr, weak(sequence_expr) evaluates to true. The …
SVA Properties I : Basics
Property defines set of behaviours of the design. To use those behaviors verification directive must be used. In other words, a property itself does not produce any result. A named property can be declared in …
SVA Sequences IV : Methods
Method .triggered This is built-in method on a sequence . This is a method to break down the complex sequence to simpler sub-sequences. The endpoint of sub-sequence can be detected using the method triggered. When …
SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence
Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators. Single delay concatenation operator (##1) zero-delay concatenation operator (##0) Single delay concatenation operator (##1)
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sequence mult_seq1; @(posedge clk1) seq1 ##1 @(posedge clk2) seq2; endsequence: mult_seq1 |
Match of mult_seq1 …
SV Event Scheduling Algorithm
While simulating System Verilog design and its test-bench including assertions, events has to be dynamically scheduled, executed, and removed as the simulator advances time. To have this feature, simulator has to maintain a data structure …
SVA Sequences III – Other Operators
Operator AND The binary operator AND is used when both operands are expected to match, but the end times of the operand sequences may be different. That means, when one of the operand sequence match, …
SVA Sequences II – Repetition Operators
There are three different kinds of repetition operators available in SVA viz., consecutive, non-consecutive and goto. For all three operators the number of iterations can be either specified by an exact count or by a …