Category Archives: Category: Verification

SVA Sequences IV : Methods

Method .triggered This is built-in method on a sequence . This is a method to break down the complex sequence to simpler sub-sequences. The endpoint of sub-sequence can be detected using the method triggered. When method triggered is evaluated in an expression, it tests whether its operand sequence has reached its end point at that

SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence

Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators. Single delay concatenation operator (##1) zero-delay concatenation operator (##0) Single delay concatenation operator (##1)

Match of mult_seq1 starts with a match of seq1 at posedge of clk1 and end with a match of seq2 at posedge clk2.

SV Event Scheduling Algorithm

While simulating System Verilog design and its test-bench including assertions, events has to be dynamically scheduled, executed, and removed as the simulator advances time. To have this feature, simulator has to maintain a data structure and usually would be a time ordered linked list. That means, at any point of time during simulation, event has

SVA Sequences III – Other Operators

Operator AND The binary operator AND is used when both operands are expected to match, but the end times of the operand sequences may be different. That means, when one of the operand sequence match, it waits for the other to match. Please note that both sequence must start at the same time.


SVA Sequences II – Repetition Operators

There are three different kinds of repetition operators available in SVA viz., consecutive, non-consecutive and goto. For all three operators the number of iterations can be either specified by an exact count or by a finite range. If the number of repetitions is specified by an exact count [*n], then ‘n’ has to be a

SVA Sequences I : Basics

Sequences Sequence is a finite list of System Verilog Boolean expressions which matches along a finite interval of consecutive clock ticks. It evaluates Boolean expressions to true in each clock tick till the last expression. The major difference of sequence from a property is that, sequence does not have a success/fail status. Instead, it simply

Code Coverage Fundamentals

Coverage is a metric to assess the progress of functional verification activity. This plays a major role to get a clear picture on how well the design has been verified and also to identify the uncovered areas in verification. Code coverage and functional coverage are the two types of coverage methods used in functional verification.

SVA : System Tasks & Functions

Assertion severity – system tasks In System Verilog, severity of assertion messages is classified by using four system tasks. These are $fatal, $error, $warning and $info. If an action block is specified, user-defined severity can be created by using these system tasks. Every assertion failure has an associated severity which can be specified in the

SVA : Concurrent Assertions

Concurrent Assertions Concurrent assertions are based on clock semantics and are evaluated continuously with every clock edge. Concurrent assertions can be temporal that means usually it describes a certain behavior that spans over a time interval. The evaluation model for concurrent assertion is based on clock and the evaluation happens only at the occurrence of

SVA : Introduction

Introduction There is a popular statement about assertion, which says “an assertion is a statement that a given property is required to hold and a directive to verification tools to verify that it does hold”. In other words, an assertion specifies a behavior of the system and it is primarily used to validate the behavior