Category Archives: Category: Verification

A glimpse on Metric Driven Verification Methodology

As the design complexity increases, the use of traditional verification methodology becomes minimal for verifying hardware designs. Directed Tests were used quite long back. Later, Coverage Driven Verification methodology (CDV) came up. In directed tests approach, verification engineer is going to state exactly what stimulus should be applied to the Design Under Test (DUT). This

Sequential Equivalence Checking for high performance design

Abstract: Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the déjà-vu situation of performance to time-to-market trade-offs; especially in high-performance designs. Sequential Equivalence Checking opens up possibilities in this area, by enabling performance-tuning related sequential micro-architectural changes to be verified with significantly lower impact on

Formal Verification – An Overview

Formal verification is a technique used in different stages in ASIC project life cycle like front end verification, Logic Synthesis, Post Routing Checks and also for ECOs. But when you go deep into it, the formal verification used for verifying RTLs is entirely different from others. There are different formal techniques available