Category Archives: Category: General

CMOS Latchup

Parasitic NPN & PNP in an inverter

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. To understand latch up we need to understand the various parasitic components in a CMOS. Let us see the CMOS cross section. Now let us introduce the parasitic transistors seen by this structure, and the effects of transients

System Verilog: Random Number System Functions

System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers. The $random verilog system function has only one random number generator shared between all threads, but each thread in simulation has its own random number generator for $urandom and $urandom_range. Separate random number generators for each thread helps to improve random stability

System Verilog : Rand & Randc

There are two type-modifier keywords available in system Verilog to declare class variable as random. Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed over their range. Variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared

Noise Margins

Noise margin is the amount of noise a circuit can withstand without compromising its operation. These values are defined so that optimization and analysis can ensure that the spurious signals are not causing any functional issues. The noise values are checked against the noise margins and if they are exceeding the margins provided, an error

System Verilog : Fork Join

The fork-join construct enables the creation of concurrent processes from each of its parallel blocks. All the blocks get the same start time and the finish time is controlled by the type of join construct used. Formal syntax for a parallel block.

With fork-join -which is available in conventional Verilog – procedure can continue

SV Constraint random value generation : Introduction

System Verilog supports three different approaches in verification as follows. 1. Directed Testing 2. Random Testing 3. Directed Random/Constrained Random Testing Directed testing is the traditional verification approach. In this case, a particular scenario is created for a known feature and set the expectation for the same. So, the features have been verified can be

SVA Basics: Bind

Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interface or a compilation unit scope. There are many ways binding can be done. Following section discusses these. Normal Bind Binding fifo to fifo_sva


What is meant by lint? It was the name originally given to a program that flagged suspicious and non-portable constructs in software programs. Later this was extended to hardware languages as well for early design analysis. That means rule checks will be applied on the developed RTLs and it helps to identify errors which we

Popular EDA Tools

Here is a list of major EDA tools for various stages of (mostly digital) design flow. These are tools considered stable and suitable for sign-off by the industry. This is what I have used or at least know people have been using them. Must have missed out niche and rare tools in use by others.