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CMOS Latchup

Latch-Up is a condition where a low impedance path is created between a supply pin and ground.

To understand latch up we need to understand the various parasitic components in a CMOS.

Let us see the CMOS cross section.
CMOS cross section with well ties

Now let us introduce the parasitic transistors seen by this structure, and the effects of transients when functioning as an inverter. The well and substrate are tapped to VDD and VSS respectively.
Parasitic NPN & PNP in an inverter

As you can see, there are two parasitic transistors formed. Lateral NPN transistor Qn’s emitter is the source of NMOS transistor, base is the P substrate, collector is the n-well of the PMOS. Similarly, for the parasitic PNP transistor Qp, emitter is the source of the PMOS, base is the n-well and collector is the substrate. If there is a voltage at the input or output of a circuit that is more positive than the supply voltage, or more negative than the ground, current flows into the gate of the transistors.
If any transient input turns on one of these transistors, it feeds the base of the other transistor and can in turn turn that ON. Since this is a feedback loop, with the collector each transistor feeding the base of the other, this can become self-sustaining. This is called latch-up.

This can be triggered in two ways:

  1. Due to a trigger, Source of NMOS is pulled below ground. The base-emitter junction voltage could then forward bias the NPN transistor Qn. This transistor will then turn ON Qp
  2. Source of PMOS transistor could be pulled above VDD. This could turn on Qp, if this goes higher than the well voltage

To cause latch-up some conditions need to be met:

  1. The product of the beta of the parasitic transistors should be 1 or greater. This can be prevented by:
    • Increasing layout spacing
    • Increasing the dopant in the base region of the transistors
  2. Well and substrate resistances should be sufficient to contribute to the voltage drop,which in turns leads to forward biasing of the transistors. To reduce the resistance to prevent latch-up:
    • Have low resistance connections to VSS/VDD
    • Add guard rings around p/n well to collect the unwanted minority carriers

Latch-ups can result in circuit malfunctioning that requires a power-down or a complete failure of the semiconductor. However, in modern processes, latch-up is not seen as an issue.

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