Scripts

Creating .lib file from verilog

Creating a dummy .lib file is something every physical design engineer has done now and then. If you have a verilog model of the block available, your task gets easier. The following script automates .lib generation from your verilog netlist. Use this as a dummy .lib to get your design flow going or use it as a template for your analog blocks for modifying the values.

Customize, edit and use. The script creates a simple Data Structre. So any modification can be done pretty easily. The script parses the verilog for the module name specified, and collects the ports & directions. In the .lib file written out, a default capacitance and transition value is specified. This is a good starting point for your blocks.

Usage: create_lib <verilog_netlist> <module_name> [transition_value] [capacitance_value]

19 Comments

19 Comments

  1. ch murali krishna

    April 17, 2014 at 6:07 pm

    Though i didn’t understand 1 piece of it but it looks great

  2. Nizam

    September 19, 2014 at 12:29 am

    Hi Sini,
    script is very good.
    I tried to run by using simple Verilog netlist.
    perl yourscript.pl
    The usage is not clean for.
    If I run ur usage I am getting create_lib is not recognized as internal or external command.
    Please help to get a dummy .lib for my simple Verilog netlist by providing execution/usage

  3. Nizam

    September 19, 2014 at 12:32 am

    its worked with perl urscript.pl verilognetlist modulename

    • mm

      Sini Mukundan

      September 19, 2014 at 8:07 am

      Nizam,

      Type ” which perl” from your terminal. In this script there is #!/usr/bin/perl at line1. Replace the /usr/bin/perl part with your “which perl” result. Then you should be able to run it without perl command.
      Sini

  4. payam

    August 9, 2015 at 2:23 am

    Dear sini
    Thank you so much for your great website.The code was very helpful.

  5. vinay kumar

    October 20, 2015 at 4:47 pm

    The script is very useful but i am getting an error
    “: bus_7_0 : input
    : bus_7_0 : input

    What changes need to be made in script to avoid this

  6. vallis

    December 8, 2015 at 8:10 am

    Dear sini
    Thank you sooo much for your code.
    It is very useful for rookie like me

    • vlsipro

      December 9, 2015 at 9:07 pm

      Glad to help.

  7. Sarath

    December 15, 2015 at 10:30 am

    Hi Sini,
    Could you please give me a perl script to reduce maxcap violations.
    If possible just give me an overview of maxcap violations and methods to reduce them.

  8. Sandeep

    February 4, 2016 at 4:54 pm

    Hi madam,
    I have a doubt in timing, if u have time just look it and give me some suggestion…
    1.How can “setup and hold” violations happen in the same path…? What are the reasons for it and how can that issue be solved?

  9. Yuvi

    June 25, 2016 at 12:12 am

    setup & hold are mutually exclusive, but they can occur for same endpoints in different corners due to variation exhibiting by std cells.

  10. Kunal

    December 14, 2016 at 5:37 pm

    Hi Sini,
    My name is Kunal Ghosh. I run online VLSI courses on https://www.udemy.com/user/anagha/

    Nice script to start with.

    I wanted to ask, if its ok to modify and use your above dummy lib generation script in one of my courses. I will acknowledge you in my course work for the same

    Hoping to collaboratively work with you

    Thanks
    Kunal

    • mm

      Sini Mukundan

      December 14, 2016 at 7:11 pm

      Hi Kunal,

      We are licensed under CC-BY-NC. While your usage might be commercial, please consider this mail as approval to use with attribution.

      Thanks,
      Sini

  11. jayant saxena

    February 20, 2017 at 3:20 pm

    i have used ur scripts to generate .lib from verilog ,its working fine but now i want to modify this script such that my .lib should also contain information of power pin eg
    pg_pin(gnd){
    pg_type : primary_ground;
    voltage_name : gnd;
    }
    pg_pin(gnds){
    pg_type : internal_ground;
    voltage_name : gnds;
    }
    pg_pin(vdd){
    pg_type : primary_power;
    voltage_name : vdd;
    }
    pg_pin(vdds){
    pg_type : internal_power;
    voltage_name : vdds;
    }
    this type of information i want to add alonfg with cell name how to do this can u tell me ?

    • mm

      Sini Mukundan

      February 21, 2017 at 9:26 pm

      You need a pattern.
      Do you have supply1/supply0 statements for you power pins in the verilog files? If so, use that for another level of parsing.

  12. Apurv

    February 25, 2017 at 8:09 pm

    Hello,
    Its great blog…
    i have one questions, can u tell me how we can extract net length from def file without loading it in tool using any perl or tcl??

    like m1 layer net length is this
    m2 layer net length is that..like wise

  13. Mahendra Reddy

    November 15, 2017 at 8:46 am

    Hi Sini,

    This script does not work if the input|output|inout signals are defined in multiple lines in the verilog.

    For example:
    input a,b,
    c;

    Script generates pin attributes only for “a” & “b” pins in .lib, but not for “c”.

    Please look into the same.

    Thanks,
    Mahendra

  14. Deepak Kartik K

    November 17, 2017 at 10:11 am

    Thank you Sini

  15. meera

    January 29, 2018 at 5:55 pm

    what is the types of .lib and can u plese explain

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