Integrated Clock Gating Cell

Clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal.Clock gating functionally requires only an AND or OR gate. Consider you were using an AND gate with clock. The high EN edge may come anytime and may not coincide with a clock edge. In that case the output of the AND gate will be a 1 for less time than the clock’s duty cycle. You in turn end up with a glitch in your clock signal.

To avoid this, a special kind of clock gating cells are used, that synchronizes the EN with a clock edge. These are call integrated clock gating cells or ICG.

There are two commonly used ICG cell types.

  • Using AND gate with high EN
    The following design uses a negative edge triggered latch to synchronize the EN signal to the CLK. The GCLK is available only when the latch o/p is high. GCLK is held low when EN is low.


  • Using OR gate with high EN

    The following design uses a positive edge triggered latch. GCLK is held high when EN is low.Note that the latch o/p is inverted at the OR input. Hence, the clock is passed through when this i/p gets a low.




    1. It wont be held another one cycle, but if the change occurred when the clock was not active, it will be held. I think the timing diagrams are a bit off. Assume the EN going low after the negative edge of the clk in the last timing diagram above.

  1. ethan

    Hi, sini,
    I got some questions about ICG,

    In posedge synchronous design, we often use AND gate with high EN.
    But the clock is held low when enable is low. Posedge FFs constitute of two latchs, clk = 0 makes the first latch toggle all the time.
    How can this power saved?


  2. Sangeetha

    Is “OR” gate based clock gating used only when driving a negative edge triggered flip flop and “AND” gate based clock gating only used for positive edge triggered flip-flops?

  3. nirmal

    Hi Sini
    In AND based clock gating, there is a possibility of clock pulse cut off before clock period. But in latch based clock gating, there is a possibility of losing a clock pulse entirely if latch setup timing is violated(meaning lath enable comes just after clock edge). Am i right?

  4. Ajay Gudi

    Hi ,
    Can you let me know how much will be fanout limit for the ICG and what should be the bit width limit also for inserting ICG.

    What is the use of inserting control point before and after the ICG ?

    Ajay Gudi

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