Multi Cycle Paths

By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that some data is captured only after a specified number of clock cycles. Till then, the data at the capturing flop will not be used. Of course your circuit should be designed in such a way for this kind of behaviour to be valid. This is usually a large combinational block between two registers. It is important to specify the multicycle paths to synthesis and place&route tools, as the tools will otherwise try to fix these paths.

This timing exception is specified by the SDC command “set_multicycle_path”. This lets you specify the number of clock cycles required for the path.

Let us take the timing path from the previous post Setup & Hold. Let us say the datapath requires 3 clock cycles.

The clock diagram is given below. Assume the launch is at edge 1 of CLK.

We can specify the timing relationship as

set_multicycle_path 3 -setup -from FF1/CP -to FF2/D

Once you have this specification, the STA tool takes the clock edge 4 as the capturing edge for FF2. By default, the hold is always checked one clock edge prior to setup edge. Hence the hold will be checked at edge 3. If you want the hold check to be done at another edge, say the launch edge itself, a set_multicycle_path -hold should also be given along with the setup specification. set_multicycle_path 1 -hold -from FF1/CP -to FF2/D will move the hold edge by one clock cycle from the default hold edge. i.e. to 2. set_multicycle_path 2 -hold will move the hold checking edge 2 cycles from the default hold edge. i.e. to clock edge 1, which is the default hold edge without any set_multicycle_path specified.


  • srinivas says:

    Good Diagrammatic illustration . Thanks

  • Vipul says:

    Good post.

    Hey Sini, can you please make a post of the internal timing operation of a D flipflop with illustrations? By internal timing operation I mean, the signal flow between gates(Say NAND if flop is designed from it). Also please explain with an example how the setup and hold margin of a flip flop is fixed.



    Loves being lazy 😛

  • mm Sini Mukundan says:

    Alright.. Will get to it sometime.

  • Rajesh.S says:

    Hi Friends,
    What about the edges where the capture edge is not considered, the signal flow may not stay constant for the remaining edges. I mean we cannot tell silicon chip that valid data will come at 4th or 5th clock edge.
    How is it really implemented in hardware.
    I think in sdc file there will no such multicycle command.

  • MUNI says:

    What happen in case of below MCP is the hold check even valid
    set_multicycle_path 3 -setup -from FF1/CP -to FF2/D

    set_multicycle_path 3 -hold -from FF1/CP -to FF2/D

  • Hezy says:

    Basic question – Why to move the hold ? By that we stress it not relax it – right?

    Tnx in advance,

    • mm Sini Mukundan says:

      Remember that hold is checking for the minimum delay. So if hold were the default previous edge to the setup constraint, it is actually a more stringent constraint. i.e. the minimum required delay in the above example with ‘set_multicycle_path 3 -setup’ will be two clock period(plus the library requirements + clock path requirement). So you might want to relax it by moving the hold check to a previous edge, depending on the path’s functionality.

  • Erik Nguyen says:

    Thanks so much !
    it is very useful.

  • vijay kumar says:

    hi sini,

    i have dought regarding zero cycle path and multi cycle path could you please explain this ?

  • Aditya Gautam says:

    I’m a fan after reading this article. 🙂
    That one image explained more than what a thousand words could’ve explained.

  • Adam says:


    I was just curious if you could give an example where you would want to move the setup check edge, but not the hold check edge. It seems to me that they should always be no more than 1 cycle off.


  • Saravanan Periasamy says:

    Hi Sini,

    I would like to know how the Multicycle paths are handled in Physical design?
    I mean that if we are having a multicycle path of 2 between the capture and launching edge, then in actual design these 2 posedges from multicycle path has to be non-functional at the capture edge(ie. capture flipflop should retain the previous value). So, are we going to add any kind of clock stretching or buffering in clock paths. ?
    Please clarify my doubt .

    • mm Sini Mukundan says:

      No. If that was the intent, you need to design for such a behaviour. When you set multicycle path in physical design, all you are saying is, look at the data only after 2 cycles.i.e. you have two cycles of clock for this path. The interim values are of no concern to PD tool.

      • Saravanan Periasamy says:

        Hi Sini,

        Then what will be the actually scenario when chip starts working ?
        Once fabrication is all done, when chip gets taped out, how these multicycle paths will be working ?

  • Saravanan Periasamy says:

    Hi Sini,

    Then what will be the actually scenario when chip starts working ?
    Once fabrication is all done, when chip gets taped out, how these multicycle paths will be working ?

  • Praveenkumar says:

    I understood what u have explained. But i have a confusion in Multi cycle path in case of two clock domains, Multi cycle paths in case of fast clock to slow clock and slow clock to fast clock. Please help me with this.

  • Thierry Dechandon says:

    Hi Sini,

    for the first time, you make me understad clearly how work set_false_path.
    For that, I salute You
    Thanks a lot for sharing knowledge.

  • vishnu says:

    so in multi-cycle paths, the hold depends on clock_period?

    • mm Sini Mukundan says:

      If you want to check for hold at any other clock edge than the launch edge, then yes. Typically you would set a multi_cycle_path to move the hold checking to launch edge. In that case, it is regular calculation, without involving clock period.

  • elias says:

    hello, please does anyone know how i can start sdc 36 proggram it because manual is confusing.

  • Amey Telang says:

    Hi Sini,

    Your post is really nice & helpful.

    But I am confused with the line ” By default, the hold is always checked one clock edge prior to setup edge.”

    Could you please explain why setup check happens at later edge & hold check happens at previous edge?

    For Ex:- Lets consider 2 flops connected one after another now does this means that hold check will be performed for 1st Flop i.e. Launch clock while setup check will be preformed for 2nd Flop i.e. Capture Clock.

    If so, what about setup check for 1st Flop & Hold Check for Second flop?

    Your explanation would really be helpful.


    • mm Sini Mukundan says:

      We are checking the hold time requirement for the path, and not a single flop.
      The check will still be performed at second flop — you are making sure that the data doesn’t reach the second flop too soon. That is why you are checking with respect to the launch edge of the clock. It should reach the second flop only after some specific time has elapsed.

  • Bijesh says:

    That was a great explanation regarding how to deal with the multicycle path in our tool. But how does the multicycle paths work in real hardware scenario? We are relaxing the timing checks in a path by setting it to be a multicycle path in the timinig analysis tool. But when it comes to the real world, the data can change in every clock cycle. But we are doing timing checks in multiple cycles only. Won’t this result in metastability issues even if our design passes timing checks?

    • mm Sini Mukundan says:

      It should be designed in such a way that those signals doesn’t get used till the second/third/nth clock period. Data can change but when it gets sampled can be controlled.

      • Bijesh says:

        Suppose we set a multicycle path such that the data at the capture end gets checked only in two clock cycles for our timing analysis. Do you mean that we should design our circuit in a way that the data change at the input of the capture flop also should not be in every clock cycle? Is it like the input data at the capture flop can change in alternate clock cycles at the max?

        • mm Sini Mukundan says:

          It’s not about when the data can change, but when it is used or sampled further along the logic. Till then the data changes are ignored.

          • Bijesh says:

            I don’t get it!!
            We set a multicycle path of 2 and if the data at the input of the capture flop changes at every clock edge, how does capture flop in the hardware know whether it has to sample the data or not??!!
            How does the capture flop know at which clock edges it has to sample the data and at which edges it need not sample the data?

          • Bijesh says:

            I think I got it. You mean that even if the data changes at the input of the capture flop in every clock cycles, the data will be stable by the time we sample it and the set up requirements can be achieved and metastablity won’t occur. Isn’t it?

  • Bijesh says:

    In which stage of the design flow we get an idea about the false paths and multicycle paths in the design?
    Which tool will report them?
    In RTL level, we are left with the logic of the design only and we will have no idea about how the tool will synthesize different paths in the design. The tool will synthesize the design according to it’s algorithm. From thousands of R2R paths the tool synthesize, how can we know that which all are false paths or multicycle paths?

    • mm Sini Mukundan says:


      Synthesize without any constraints except for the clocks. (Provided you have real false paths in your design).
      Don’t even set false paths between the clocks even if they are asynchronous to each other. Report the timing.

      The designer can understand from the reports — say a path from CLK1 to CLK2 isn’t a real path and needn’t be optimized to meet timing. And so on.

      So the answer to your question is, the designer should know. The tool may synthesize the RTL in multiple ways, but the reports should give you a clue.

  • Bijesh says:

    When we cross from a faster clock domain to slower domain, we use an asynchronous FIFO to avoid data loss due to slower sampling rate at the receiving clock domain. But somewhere I read about setting multicycle path and false path in CDC.

    When there is an asychronous FIFO (which we normally use to prevent data loss), how does there come a multicycle path or false path? I ask this because, when we write data into the asynchronous FIFO, the data input to the FIFO and FIFO write clock are in same clock. So no clock domain crossing occurs at this point. When we read data from the FIFO, the read clock and the data fed circuit will be in same clock domain. Again, no clock domain crossing!! Please correct me if I am wrong!!

  • gireesh says:

    why long wire length is independent of scaling factor .we are only scaling the length, width,thickness of the short wire. for long wire we scale only width and thickness

  • Hemal says:

    Thank you Sini, for knowledge sharing.

  • Vinay H M says:

    IF launching clock and capturing clock are having different frequencies and lets assume setup check is done after 3 clock cycles. for this condition what could be the proper command?

    • mm Sini Mukundan says:

      If you want to capture at edge 3 of Clk2 and to ensure hold is checked at edge 1 of Clk2,
      set_multicycle_path -setup 2 -from Clk1 -to Clk2
      set_multicycle_path -hold 1 -from Clk1 -to Clk2

      For edge 4,
      set_multicycle_path -setup 3 -from Clk1 -to Clk2

  • anonymus says:

    what happens instead of multicyclepath …. inserting flop b/w the logic(making 2 reg-reg paths)…. pros and cons ?

  • NAKUL P C says:

    Hi Sini,
    I would like to know how we are implementing the checking of hold in different edges? Suppose i want to check on second edge, how we implement it?

    • mm Sini Mukundan says:

      If you have set a multicycle path check on setup, hold also moves to the previous edge to the setup check edge.

      I am assuming you are talking about STA, and not RTL implementation.

  • Badarinath says:

    can you provide a sample setup and hold timing report of a multi cycle path which shows the launch and capture edges?

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