Metastability
In digital circuit, the signal is required to be within certain voltage or current limits (logic 0/1 levels) for correct circuit operation. If the signal is within an intermediate range… Read more »
In digital circuit, the signal is required to be within certain voltage or current limits (logic 0/1 levels) for correct circuit operation. If the signal is within an intermediate range… Read more »
We have seen the command “uplevel” and how to use it earlier. Now, let’s look into a related command upvar. Syntax The TCL language reference manual gives the following description… Read more »
uplevel is a built-in tcl command that evaluates a script in a different level. Syntax uplevel ?level? arg ?arg …? level here can be number or a # followed by… Read more »
Many a time your chip is overdesigned due to undue pessimism in timing calculations. Pessimism in timing analysis makes it difficult for designs to close timing and it is imperative… Read more »
For clock trees, the traditional way is to go with zero skew or balanced skew. For each of the sinks, the insertion delay is kept to be equal so that… Read more »
Let us continue with the physical only cells present in the standard cell libraries that ease the digital PD flow. Filler Cells Well Tap Cells Decap Cells Filler Cells Once… Read more »
In PD flow, you must have come across the term physical only cells. Let us explore a few of them. Well Tap Cells Decap Cells Filler Cells Well Tap Cells… Read more »
Latch-Up is a condition where a low impedance path is created between a supply pin and ground. To understand latch up we need to understand the various parasitic components in… Read more »
As we saw in the earlier article on ICG, a gated clock is when you use a logic gate to control or enable to the propagation of clock to certain… Read more »
In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV,… Read more »