Standard Delay Format

SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF now has the delay numbers derived from these as well as the cell delays associated with the digital cells. SDF or Standard Delay Format is an IEEE specification. SDF is an ASCII format

Multi Cycle Paths

By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that some data is captured only after a specified number of clock cycles. Till then, the data at the capturing flop will not be used. Of course your circuit should be designed in such

STA – Setup and Hold Time Analysis

It is easy to get confused with the definitions of setup and hold violations. We are used to the definitions of setup and hold times for a single flipflop. The setup and hold violation checks done by STA tools are slightly different. PT aptly calls them max and min delay analysis. However, the other terminology

SVA Properties II : Types

Sequence Properties Properties which contain sequence definitions are called sequence properties.Sequence properties are of three types. weak(sequence_expr) If there is no finite prefix that witnesses inability to match the sequence_expr, weak(sequence_expr) evaluates to true. The following example shows a weak sequential property p1.

An evaluation attempt of weak_assert assertion returns true in the following

SVA Properties I : Basics

Property defines set of behaviours of the design. To use those behaviors verification directive must be used. In other words, a property itself does not produce any result. A named property can be declared in module, interface, program, clocking block, package, compilation-unit scope, generate block or checker. In simulation run, property will be either in

Synchronous & Asynchronous Reset

Reset Reset is a signal that is used to initialize the hardware, as the design does not have a way to do self initialization. That means, reset forces the design to a known state. In simulation, usually it is activated at the beginning, but in real hardware, reset is usually activated to power up the

SVA Sequences IV : Methods

Method .triggered This is built-in method on a sequence . This is a method to break down the complex sequence to simpler sub-sequences. The endpoint of sub-sequence can be detected using the method triggered. When method triggered is evaluated in an expression, it tests whether its operand sequence has reached its end point at that

SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence

Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators. Single delay concatenation operator (##1) zero-delay concatenation operator (##0) Single delay concatenation operator (##1)

Match of mult_seq1 starts with a match of seq1 at posedge of clk1 and end with a match of seq2 at posedge clk2.

SV Event Scheduling Algorithm

While simulating System Verilog design and its test-bench including assertions, events has to be dynamically scheduled, executed, and removed as the simulator advances time. To have this feature, simulator has to maintain a data structure and usually would be a time ordered linked list. That means, at any point of time during simulation, event has

Clock Jitter

In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock jitter is a characteristic of the clock source and the clock signal environment. It can be defined as “deviation of a clock edge from its ideal location.” Clock jitter is typically caused by