SVA Sequences IV – Multiple Clock Domains/ Multi-clocked Sequence

Multi-clocked sequences are built by concatenating multiple single clocked sequences in different clock domains using following operators. Single delay concatenation operator (##1) zero-delay concatenation operator (##0) Single delay concatenation operator (##1)

Match of mult_seq1 …

Clock Jitter

In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock jitter is a characteristic of the clock source and the clock signal environment. …

set_clock_uncertainty

There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means. The SDC manual states that set_clock_uncertainty Specifies the uncertainty or skew characteristics of a single clock or between two …