Insertion Delay & set_clock_latency

Clock latency refers to the delay that is assumed to exist between the clock source and the flip-flop clock pin. This is typically used before layout, when clock is ideal. It is not the actual delay, but the delay specified by the user, to account for the clock network delay after implementation. There are two


There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means. The SDC manual states that set_clock_uncertainty Specifies the uncertainty or skew characteristics of a single clock or between two different clocks. The timing analyzer uses this information to determine the worst possible clock arrival times for each timing check.

SVA Sequences III – Other Operators

Operator AND The binary operator AND is used when both operands are expected to match, but the end times of the operand sequences may be different. That means, when one of the operand sequence match, it waits for the other to match. Please note that both sequence must start at the same time.


Hamming Code

In data transmission, error detection is required as there are high chances of having bit changes in the data. Hamming code is a linear error-detecting and correcting code invented by R. W. Hamming. It can detect up to 2 bit errors (simultaneous) and can correct single bit error. The key concept in Hamming code calculation

SVA Sequences II – Repetition Operators

There are three different kinds of repetition operators available in SVA viz., consecutive, non-consecutive and goto. For all three operators the number of iterations can be either specified by an exact count or by a finite range. If the number of repetitions is specified by an exact count [*n], then ‘n’ has to be a

Physical Design Flow V: Physical Verification

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis IV. Routing After routing, your layout is complete. Now a number of checks are performed to verify that the drawn layout works as intended. Physical verification Equivalence Checking Timing Analysis Equivalence check will compare the netlist we started out with (pre-layout/synthesis netlist) to the netlist

SVA Sequences I : Basics

Sequences Sequence is a finite list of System Verilog Boolean expressions which matches along a finite interval of consecutive clock ticks. It evaluates Boolean expressions to true in each clock tick till the last expression. The major difference of sequence from a property is that, sequence does not have a success/fail status. Instead, it simply

Code Coverage Fundamentals

Coverage is a metric to assess the progress of functional verification activity. This plays a major role to get a clear picture on how well the design has been verified and also to identify the uncovered areas in verification. Code coverage and functional coverage are the two types of coverage methods used in functional verification.

Physical Design Flow IV:Routing

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis After CTS, the routing process determines the precise paths for interconnections. This includes the standard cell and macro pins, the pins on the block boundary or pads at the chip boundary. After placement and CTS,the tool has information about the exact locations of blocks, pins

Physical Design Flow III:Clock Tree Synthesis

I. NetlistIn & Floorplan II. Placement For synchronized designs, data transfer between functional elements are synchronized by clock signals. In a top level digital design, you will have one more more clock sources, like PLLs or oscillators within the chip. You may also have an external clock source connection through an IO. For a digital