Physical Design Flow II:Placement

I. NetlistIn & Floorplan After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to let the tool to do standard cell placement. The tool determines the location of each of the components (in digital design, standard cell instantiations) on

Physical Design Flow I : NetlistIn & Floorplanning

This is going to be a series of step-by-step explanation of physical design flow for the novice. I am going to list out the stages from Netlist-GDS in this session. Of course some say synthesis should also be part of physical design, but we will skip that for now. So, you have completed your RTL,


set_timing_derate set_timing_derate is a command that lets you constraint the timing a bit more. The idea and application is simple enough, but you might get confused with all the talk about process variation and OCV whenever someone starts on derate. Best option is, forget the OCV. Let’s uncomplicate and first see how the command works.

SVA : System Tasks & Functions

Assertion severity – system tasks In System Verilog, severity of assertion messages is classified by using four system tasks. These are $fatal, $error, $warning and $info. If an action block is specified, user-defined severity can be created by using these system tasks. Every assertion failure has an associated severity which can be specified in the

SVA : Concurrent Assertions

Concurrent Assertions Concurrent assertions are based on clock semantics and are evaluated continuously with every clock edge. Concurrent assertions can be temporal that means usually it describes a certain behavior that spans over a time interval. The evaluation model for concurrent assertion is based on clock and the evaluation happens only at the occurrence of

SVA : Introduction

Introduction There is a popular statement about assertion, which says “an assertion is a statement that a given property is required to hold and a directive to verification tools to verify that it does hold”. In other words, an assertion specifies a behavior of the system and it is primarily used to validate the behavior

Creating .lib file from verilog

Creating a dummy .lib file is something every physical design engineer has done now and then. If you have a verilog model of the block available, your task gets easier. The following script automates .lib generation from your verilog netlist. Use this as a dummy .lib to get your design flow going or use it


Engineering Change Order or ECO is how you incorporate last minute changes in your design. ECO saves money and time and is prevalent in the industry. When I talk ECO, I am talking about ECOs in the layout. So typically you start with an ECO on the gate level netlist. The designer need to edit

A glimpse on Metric Driven Verification Methodology

As the design complexity increases, the use of traditional verification methodology becomes minimal for verifying hardware designs. Directed Tests were used quite long back. Later, Coverage Driven Verification methodology (CDV) came up. In directed tests approach, verification engineer is going to state exactly what stimulus should be applied to the Design Under Test (DUT). This

Spare Cells

I have been writing an article on ECO flows.Of course I cannot talk about freeze_silicon ECOs without talking about spare cells.When I was a wee intern sitting through PnR training, spare cells confused me. I thought I had to insert the spares and use them in the same session! So here’s a small note about