Popular EDA Tools

Here is a list of major EDA tools for various stages of (mostly digital) design flow. These are tools considered stable and suitable for sign-off by the industry. This is what I have used or at least know people have been using them. Must have missed out niche and rare tools in use by others. Please leave a comment if I missed some important tools!

Area Cadence Synopsys Mentor Graphics Others
Virtual Prototying Virtual System Platform [VSP] VaST CoMET and METeor, Virtualizer Vista
RTL Linting, Clock Tracing, Constraint generation Incisive HAL Leda RTL Checker Spyglass [Atrenta], Fishtail Focus
Digital Simulation Incisive – NcSim VCS Questasim
Analog Simulation Incisive – AMS CustomSim Questa ADMS
Circuit Simulation Spectre Hspice (accurate), Hsim (Fast) Eldo Classic
Formal Verification[Property Checking] IFV [Incisive Formal Verifier] Magellan OneSpin[OSS]
Formal Verification[Equivalence Checking] Conformal LEC Formality FormalPro OneSpin[OSS]
Testbench Qualification Certitude
Debugging Incisive [SimVision] Verdi [SpringSoft] Questa
Multi-voltage rule checker Conformal Low Power MVRC
Clock-Domain Crossing (CDC) Verification Conformal Constraint Designer Questa CDC Spyglass [Atrenta], Meridian [Real Intent]
e-testbench Specman
Regression Manager vManager CustomExplorer Ultra Questa Verification Manager
Logic Synthesis RTL Compiler [RC] Design Compiler Intuitive
Place & Route Encounter (EDI) IC Compiler Olympus
Static Timing Analysis Encounter Timing System[ETS] Prime Time [PT]
Extraction QRC StarRC XT Calibre xRC
Automatic test pattern generation TrueTime ATPG TetraMax FastScan
Physical Verification Assura Hercules Calibre
Power Analysis EPS Prime Time – PX
Rail Analysis EPS Prime Rail


  1. Jaimin Panchal

    June 3, 2013 at 3:54 pm


    Nice information Gathered by you.

    Please put some more practical and theoretical information as well.

    i am currently pursuing Physical design (back end) from private institute in Ahmadabad,Gujarat,India.

    I would like you to share some more information.i will share some of the data that i have.

    please take some time and let me know what we can do to share the knowledge.



  2. manjunath

    August 19, 2013 at 9:14 am

    RTL Linting – Cadence -Tool is HAL

    • samba siva ra0

      September 25, 2014 at 3:15 pm

      Please help me in launching cadence HAL linting tool in linux machine

      • mm

        Sini Mukundan

        September 25, 2014 at 3:22 pm

        The command is “hal”

        e.g. hal file.v

  3. sharan

    September 17, 2014 at 12:38 pm

    ASIC flow
    Simulation and verification – VCS
    Linting -Leda
    Sythesis – Design Compiler(DC)
    Physical Design – IC compiler(ICC)
    DRC and LVS – Hercules
    Parasatic Extraction – StarRC
    DFT – Tetramax for ATPG
    – DC can insert DFT
    Mutli voltage simulation – Multi voltage Simultor
    UPF checks – MVRC

    Correct me if I am wrong

  4. Tahraoui

    June 15, 2015 at 9:05 pm

    hi all
    i need to have some docs about POCV & AOCV.
    thank you

  5. Jagadish KG

    July 25, 2015 at 7:44 pm


    In the 4th row, you might need to change it to Analog and Mixed Signal Simulation. And in 5th row you can change the Circuit simulation to Analog Simulation or Spice simulation.


  6. Prof. Pramod Borole

    September 14, 2015 at 2:12 pm

    I have introduced new subject at Post graduate level viz. Nano logic Design that includes design of Nano digital ICs, SET quantum devices. Please give me a list of tools for nanalogic design

    • mm

      Sini Mukundan

      September 15, 2015 at 9:20 am

      We don’t have any experience with nano logic designs.

  7. Anil

    February 1, 2017 at 10:44 am

    RTL compiler for logic synthesis is obsolete tool from cadence. now the present tool is “Genus synthesis Solution”. BTW, I dont know how the clock tracing and constraint generation is done with HAL. give some commands .

  8. Pradeep Purushothaman Vadakkodathu

    June 8, 2017 at 11:07 pm

    Sini excellent information! thanks. Can I know whether Tanner EDA can be used for any part of IC designing? It has different tools like S-Edit L-EDIT n some LVS etc. If possible please give an explanation for each tool and the design flow in it. Thanks in advance!.

    • mm

      Sini Mukundan

      June 9, 2017 at 10:25 am

      We do not have any experience using these tools. Please contribute if you can in expanding the list.

  9. darni

    October 6, 2017 at 9:18 am

    I am newbie, I have heared none of these softwares, but have worked in cadence virtuoso and orcad.
    Virtuoso is used to design at transistor level IC design
    Orcad is component level circuit design

    Correct me if wrong

    Back end design I will learn soon

  10. Sumi

    May 11, 2018 at 4:01 pm

    Orcad is for board level design. The above mentioned tools are for VLSI/ASIC design/verification

  11. Vamsi

    September 28, 2018 at 10:55 am


    then what about Innovus tool, for what purpose Innovus is used and by which company.

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