Popular EDA Tools

Here is a list of major EDA tools for various stages of (mostly digital) design flow. These are tools considered stable and suitable for sign-off by the industry. This is what I have used or at least know people have been using them. Must have missed out niche and rare tools in use by others. Please leave a comment if I missed some important tools!

Area Cadence Synopsys Mentor Graphics Others
Virtual Prototying Virtual System Platform [VSP] VaST CoMET and METeor, Virtualizer Vista
RTL Linting, Clock Tracing, Constraint generation Incisive HAL Leda RTL Checker Spyglass [Atrenta], Fishtail Focus
Digital Simulation Incisive – NcSim VCS Questasim
Analog Simulation Incisive – AMS CustomSim Questa ADMS
Circuit Simulation Spectre Hspice (accurate), Hsim (Fast) Eldo Classic
Formal Verification[Property Checking] IFV [Incisive Formal Verifier] Magellan OneSpin[OSS]
Formal Verification[Equivalence Checking] Conformal LEC Formality FormalPro OneSpin[OSS]
Testbench Qualification Certitude
Debugging Incisive [SimVision] Verdi [SpringSoft] Questa
Multi-voltage rule checker Conformal Low Power MVRC
Clock-Domain Crossing (CDC) Verification Conformal Constraint Designer Questa CDC Spyglass [Atrenta], Meridian [Real Intent]
e-testbench Specman
Regression Manager vManager CustomExplorer Ultra Questa Verification Manager
Logic Synthesis RTL Compiler [RC] Design Compiler Intuitive
Place & Route Encounter (EDI) IC Compiler Olympus
Static Timing Analysis Encounter Timing System[ETS] Prime Time [PT]
Extraction QRC StarRC XT Calibre xRC
Automatic test pattern generation TrueTime ATPG TetraMax FastScan
Physical Verification Assura Hercules Calibre
Power Analysis EPS Prime Time – PX
Rail Analysis EPS Prime Rail

13 Comments

  1. Hi,

    Nice information Gathered by you.

    Please put some more practical and theoretical information as well.

    i am currently pursuing Physical design (back end) from private institute in Ahmadabad,Gujarat,India.

    I would like you to share some more information.i will share some of the data that i have.

    please take some time and let me know what we can do to share the knowledge.

    Thanks.

     

  2. sharan

    ASIC flow
    Simulation and verification – VCS
    Linting -Leda
    Sythesis – Design Compiler(DC)
    Physical Design – IC compiler(ICC)
    DRC and LVS – Hercules
    Parasatic Extraction – StarRC
    DFT – Tetramax for ATPG
    – DC can insert DFT
    Mutli voltage simulation – Multi voltage Simultor
    UPF checks – MVRC

    Correct me if I am wrong

  3. Jagadish KG

    Hi,

    In the 4th row, you might need to change it to Analog and Mixed Signal Simulation. And in 5th row you can change the Circuit simulation to Analog Simulation or Spice simulation.

    Regards,
    Jagadish

  4. Anil

    RTL compiler for logic synthesis is obsolete tool from cadence. now the present tool is “Genus synthesis Solution”. BTW, I dont know how the clock tracing and constraint generation is done with HAL. give some commands .

  5. Pradeep Purushothaman Vadakkodathu

    Sini excellent information! thanks. Can I know whether Tanner EDA can be used for any part of IC designing? It has different tools like S-Edit L-EDIT n some LVS etc. If possible please give an explanation for each tool and the design flow in it. Thanks in advance!.

  6. darni

    I am newbie, I have heared none of these softwares, but have worked in cadence virtuoso and orcad.
    Virtuoso is used to design at transistor level IC design
    Orcad is component level circuit design

    Correct me if wrong

    Back end design I will learn soon

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