Physical Design

SPEF Files Explained

Standard Parasitic Exchange Format(SPEF) is an IEEE format for specifying chip parasitics. The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System . Latest version of SPEF is part of 1481-2009 IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA) . The SPEF provides a standard medium to pass parasitic information between EDA tools during any stage in the design process.


  1. All keywords in SPEF start with an asterisk (*), followed by all capital or underscore. e.g. *D_NET
  2. Keywords, identifiers, characters, and numbers are delimited by syntax characters, white_space, or newline.
  3. Any character other than alphanumerics and underscore (_) shall be escaped when used in an identifier in a SPEF file. However there are exceptions to the escape rule as follows:
    1. The pin_delim (*DELIMITER) between an instance and pin name, such as : in I\$481:X
    2. The heir_delim (*DIVIDER) character, such as / in /top/coreblk/cpu1/inreg0/I\$481
    3. A prefix_bus_delim or suffix_bus_delim (*BUS_DELIMITER) being used to denote a bit of a logical bus or an arrayed instance, such as DATAOUT[12]
  4. SPEF file synatx is SPEF_file ::= header_def [name_map] [power_def] [external_def] [define_def] [variation_def] internal_def
    A spef file can have the follwing sections

    • Header Section : header_def
    • Name map definition : [name_map]
    • Power & Ground Nets definition : [power_def]
    • External definition : [external_def]
    • Hierarchical SPEF (entities) definition : [define_def]
    • Process and temperature variation definition : [variation_def]
    • Internal definition : internal_def

    Not all of these are mandatory, and I will be talking in detail about a typical SPEF file that has a header section, name_map, ports section(external_def) and the parasitic definition section(internal_def).

  5. // begins a single-line comment anywhere on the line, which is terminated by a newline. /* begins a multiline comment, terminated by */

Header Section
The header section has information on design_name, extrcation tool, units etc. Some of the keywords in header are given below.
– Spef version : *SPEF
– Design Name: *DESIGN
– RC EXtrcation tool : *PROGRAM
– Hierarchy delimiter : *DIVIDER
– Bus delimiter : *DELIMITER
– Units : *T_UNIT ,*C_UNIT , *R_UNIT, *L_UNIT

Name map definition
Name map section starts with the Keyword “*NAME_MAP”. This is an optional section, and is used to reduce the filesize by mapping the long names into shorter numbers preceeded by an asterisk. (*).

Subsequently in the parasitic definition sections, o_vcm0_s[0] will be referred by *1 and so on.

External definitions (*PORTS)
We are interested in the ports as defined by the SPEF. Search for *PORTS in the spef file.

When read together with the name map section, this means o_vcm0_s[0] & o_vcm0_b[2] are output ports, whereas i_comp_etot & i_comp_lat_ehpf are an input ports of the design as specified by the *DESIGN construct.

Internal Definition
This section gives detailed net definition OR reduced net definition. After the *PORTS section, you will usually have a *D_NET statement. If it is an *R_NET , you have a reduced net definition. I am going to explain the *D_NET in this section, as it is the most common in design flow.

The syntax for *D_NET specification is d_net ::= *D_NET net_ref total_cap [routing_conf] [conn_sec] [cap_sec] [res_sec] [induc_sec] *END

A typical example is

  • The *D_NET *214 9.90410 line refers to the netname and the total cap of the net. Looking up *214 in name_map section gives the net name as i_comp_lat_ehpf.
  • The *CONN section gives the external & internal connection to the net. Connection to a port is an external connection and is denoted by *P. An internal connection is to the pin of a cell and start with an *I.
    Syntaxc: conn_def ::= *P external_connection direction {conn_attr} | *I internal_connection direction {conn_attr}

    • *P *214 I : This means the direction is input. Can have I, O or B, depending on whther the port/pin is input, output or bidirectional.
    • *C 0.00000 91.0500 : Gives the coordinates
    • *L gives the capacitance load value. If a driver, *D will give the driving cell name.

    The snippet

    gives the connections of the D_NET *214 as port *214 and *5916:A. From name_map section, *5916 is mapped to the instance U67. So are looking at the parasitics of net i_comp_lat_ehpf which has port i_comp_lat_ehpf as the driver and a single fanout of U67/A. The load cap as seen by the net at pin U67/A is 7.70000(unit as specified in *C_UNIT).
  • The *CAP definition gives detailed capacitance of the net. If lumped to ground, the cap_elem has only one node, but can have two nodes if coupled capacitance. The example above is for capacitance lumped to ground.
    Cap element 1 is for the node *214 (i_comp_lat_ehpf) , and it has a capacitance of 7.56297units. The capacitance section will grow with the number of fanouts.
  • *RES Section
    The *RES section provides the resistance for the net. 1 *214 *5916:A 20.1528 specifies that between the nodes *214 and *5916:A, the resiatnce is 20.1528units(as specified by *R_UNIT). The resiatnce section will grow with the number of fanouts.
  • *END denotes the end of parasitic definition for the *D_NET. The *D_NET section for the next net starts after the *END statement.


  1. Shekhar Dandavate

    June 16, 2013 at 12:28 pm


    You have very nicely explained the spef syntax.

    Thank you.,


  2. Vinod

    July 3, 2013 at 6:59 am

    Very nicely explained. Thank you.

  3. Nandish

    March 28, 2014 at 1:40 pm

    In my SPEF file, I’m getting below mentioned lines:
    0 CLK_BAR:16 M0:g 2.646e-05
    1 CLK_BAR:2 VDD:33 2.47461e-05

    But, in my SPICE file, there are no nodes with numbers 16 and 2. I’m using MentorGrahics IC PEX to extract parasitic. You have given such a great article. I hope you would help me out here.

  4. Sini

    April 1, 2014 at 2:29 pm

    Sorry, don’t have an answer for you right now.  Have to see an example.

  5. Pratik

    July 30, 2014 at 12:32 pm

    Hi Sini,

    Thanks for explaining in details.
    I have a question, In my SPEF I have:

    *D_NET *563502 14.7389
    *P clk_cpu I *C 2453.7 694.4
    *I *2393:I I *C 2454.1 611.6 *D CKBD16
    *I *2392:I I *C 2455.1 652.2 *D CKND16
    *I *2394:I I *C 2456.9 690.4 *D CKBD12

    So why input instance has *D information, As per I understood from blog, it should be *L.

    Would you please let me know about this?
    Pratik Shah.

    • mm

      Sini Mukundan

      July 30, 2014 at 1:23 pm

      I have seen these with QRC extraction tool and StarRC writes out the format with *L. Maybe dependent on the tool you use.

      In “*I *2393:I I *C 2454.1 611.6 *D CKBD16″, the load cap is not explicitly mentioned, but if you trace, *2393 will be of type CKBD16. It is the case for all these *D statements. I haven’t verified the numbers in STA, but I bet the “capacitance” value in the .lib for the pin “I” of this cell will be used as the load capacitance.

  6. Pratik

    July 30, 2014 at 2:40 pm

    Thanks Sini,

  7. Aalok

    November 25, 2014 at 5:25 pm

    hello Siri, following your pages from quite sometime, and it is of great help for someone like me who has just started his career in VLSI industry 🙂
    i have got a doubt regarding the content of SPEF file.
    under *CAP and *RES, i see something like this.

    1 *19:shift 0.0203868
    2 *20:shift *19:q 0.00208171
    3 *20:shift *20:d 0.0744220
    4 *20:shift 0.103023

    1 *9 *20:shift 1.36540
    2 *19:shift *20:shift 3.72776
    3 *19:shift *9:36 0.00100000
    4 *20:shift *9:42 0.00100000

    can you tell me what these ‘shift’ really mean?
    we use StarXT for parasitic extraction. thanks in advance 🙂

    • Sini

      November 26, 2014 at 9:30 am

      How is the *D_NET section? Is shift by any chance a pin of instance *19?

  8. Aalok

    November 26, 2014 at 10:48 am

    *P *9 I *C 5.36489 0.424889
    *I *19:shift I *C 3.27489 0.449889
    *I *20:shift I *C 10.3049 0.449889

    now it is clear 🙂 ‘shift’ is after all a pin of instace *19 and *20… i hadn’t given enough thought on this i suppose 🙂 thanks again

  9. Sanath Ali

    March 4, 2015 at 11:41 am

    Hello Sini,

    1 *1:2 0.459127
    2 *1:3 2.50345

    In the above statement, I understand it is a lumped cap of *1 node. I want to know what is *1:2 or *1:3 refers to?

    • mm

      Sini Mukundan

      March 5, 2015 at 7:46 am

      *1 above is a net. Look in the *NAME_MAP section for the name of *1.

      *1:2 and *1:3 are the nodes(or branches) created by the extraction tool for net *1.Most of the times these are actual routing layer changes. Or fractured by the tool.

  10. Sophia

    July 17, 2015 at 1:33 pm


    Thanks for your explanation. It’s clear and helpful.
    Meanwhile, could you please also share *|S and *|N ?

    I saw them in my SPEF file

  11. anoop

    October 14, 2015 at 1:14 pm

    your articles are super helpful for interns like me thanks a lot

  12. senthilvelan

    November 2, 2015 at 10:11 am

    nice article .

  13. chaitali

    January 21, 2016 at 10:17 am

    If possible please explain the intermidiate steps also i.e power_def define_def and variation_def

  14. Himanshu Gautam

    June 6, 2016 at 5:03 pm

    If I have a netlist of a design which I have made, now I want to have a spef of that design. My first question is, if that could be done? Second, if yes then how could it be done?

  15. Tia

    August 18, 2016 at 11:23 pm

    What role does pin plays at the time of RC extraction?

  16. kartus

    October 9, 2017 at 10:30 am

    While fixing erc in primetime, i got an error that {{ ” Expected boolean value but got “false false”. }}. Please can you tell me what may be the issue?

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