Recovery and Removal Checks

Recovery and removal analysis are done on asynchronous signals like resets. These specify the requirement of these signals with respect to clock.Recovery Time is the minimum required time to the next active clock edge the after the reset (or the signal under analysis) is released. Similarly, Removal Time is the minimum required time after the clock edge after which reset can be released. You are trying to make sure that the reset removal is not occurring for different flops for different clock edges, thereby creating functional/metastability issues.
recovery-removal
For the clock edges A & B, Tr is the recovery time, and Tm is the removal time. RESET cannot be released within these intervals.

recovery_violation
Here, reset_n is applied in the beginning and after edge A, it is released. However, the clock edge B comes too soon after the reset_n release. (The release is within the Tr of edge B). Hence this is a case of recovery violation. Similarly, if the reset_n was released within the Tm time range, it would be a removal violation. You can see that recovery time is like the setup check, in that this is the time the asynchronous input should be stable before the arrival of the clock. Similarly removal is the equivalent of hold check, in that the asynchronous input should be held after the clock edge.

Let let us see how to read the timing reports. Given below is an example schematic. Look up the drill from Setup & Hold .

recovery_removal

Recovery Slack = Data Required Time – Data Arrival Time

Data Arrival Time = Clock Network Delay to FF1 + Combination path delay to CLR of FF2.
Data Required Time = Clock period + Clock Network Delay to FF2/CP – Tr of FF2.

For ideal clock, Tr is the time before the next clock edge the CLR input should be stable. This library removal time for CLK-CLR arc will be given in the .lib.

Removal check is similar to the hold check explained here. You are checking this at the same clock edge, if the path is between two flip flops.

Removal Slack = Data Arrival Time – Data Required Time

Data Arrival Time = Clock Network Delay to FF1/CP + Combination path delay from FF1/Q to FF2/CLR
Data Required Time = Clock Network Delay to FF2/CP + Tm of FF2
The library requirements will be available in the .lib file. Again, assuming ideal clock, the CLR input should not reach the FF2/CLR at least before the library removal requirement.

Sini Mukundan

Sini Mukundan

Staff Engineer at Texas Instruments
Sini is an expert on physical design flow and related methodologies. Outside work, she is an avid reader and generally loves being lazy.
Sini Mukundan

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9 Comments

  1. abeaut

    Hi,

    Thanks for the post. It doesn’t make sense from your explanation and the timing report. The checks are for synchronous signals and not for asynchronous ones.

    You will violate setup/hold times for asynchronous signals, that is the reason you need synchronizers.

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