STA

Recovery and Removal Checks

Recovery and removal analysis are done on asynchronous signals like resets. These specify the requirement of these signals with respect to clock.Recovery Time is the minimum required time to the next active clock edge the after the reset (or the signal under analysis) is released. Similarly, Removal Time is the minimum required time after the clock edge after which reset can be released. You are trying to make sure that the reset removal is not occurring for different flops for different clock edges, thereby creating functional/metastability issues.
recovery-removal
For the clock edges A & B, Tr is the recovery time, and Tm is the removal time. RESET cannot be released within these intervals.

recovery_violation
Here, reset_n is applied in the beginning and after edge A, it is released. However, the clock edge B comes too soon after the reset_n release. (The release is within the Tr of edge B). Hence this is a case of recovery violation. Similarly, if the reset_n was released within the Tm time range, it would be a removal violation. You can see that recovery time is like the setup check, in that this is the time the asynchronous input should be stable before the arrival of the clock. Similarly removal is the equivalent of hold check, in that the asynchronous input should be held after the clock edge.

Let let us see how to read the timing reports. Given below is an example schematic. Look up the drill from Setup & Hold .

recovery_removal

Recovery Slack = Data Required Time – Data Arrival Time

Data Arrival Time = Clock Network Delay to FF1 + Combination path delay to CLR of FF2.
Data Required Time = Clock period + Clock Network Delay to FF2/CP – Tr of FF2.

For ideal clock, Tr is the time before the next clock edge the CLR input should be stable. This library removal time for CLK-CLR arc will be given in the .lib.

Removal check is similar to the hold check explained here. You are checking this at the same clock edge, if the path is between two flip flops.

Removal Slack = Data Arrival Time – Data Required Time

Data Arrival Time = Clock Network Delay to FF1/CP + Combination path delay from FF1/Q to FF2/CLR
Data Required Time = Clock Network Delay to FF2/CP + Tm of FF2
The library requirements will be available in the .lib file. Again, assuming ideal clock, the CLR input should not reach the FF2/CLR at least before the library removal requirement.

11 Comments

11 Comments

  1. DMohanty

    July 15, 2014 at 8:13 pm

    In my opinion during recovery and removal check the reference signal is asynchronous signal,correct me if i am wrong.

  2. Sini

    July 21, 2014 at 8:14 pm

    You are checking the asynchronous signal, with respect to the clock.

  3. balu

    July 22, 2014 at 12:02 pm

    Hi, How do you make sure that the reset pin will not fall in that period, because it might trigger at anytime?..(like the reset pin in any device)

    • mm

      Sini Mukundan

      July 30, 2014 at 4:06 pm

      It is design dependent.

  4. abeaut

    August 5, 2014 at 8:06 am

    Hi,

    Thanks for the post. It doesn’t make sense from your explanation and the timing report. The checks are for synchronous signals and not for asynchronous ones.

    You will violate setup/hold times for asynchronous signals, that is the reason you need synchronizers.

  5. xuhaoee

    September 24, 2014 at 11:29 am

    i think every asic using an asynchronous reset should include a reset synchronizer circuit!

  6. koushik

    January 8, 2015 at 9:44 pm

    can you please let me know about stuck at fault analysis

  7. Puneeth

    October 12, 2015 at 12:25 pm

    Hi ,
    Can you please explain regarding timing analysis with multiple clocks.

  8. Dhivakar

    April 3, 2016 at 1:37 am

    hi
    is there any command for fixing hold violation meanwhile no take any action on set violation(in encounter tool)

  9. Suresh

    February 7, 2017 at 12:06 pm

    Hi,
    Thanks for your examples.
    What would be the problem if we model recovery checks are setup checks in .lib ?
    Does it create problem during STA?

  10. kakungulu

    February 7, 2017 at 8:51 pm

    Regarding a low-active reset signal, is it normal to have removal and recovery checks for both rise and fall?

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