Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the déjà-vu situation of performance to time-to-market trade-offs; especially in high-performance designs. Sequential Equivalence Checking opens up possibilities in this area, by enabling performance-tuning related sequential micro-architectural changes to be verified with significantly lower impact on effort estimates and risk. This nascent technology promises to change the way we look at eleventh hour changes.
With ever increasing design performance requirements and complexity thereof coupled with the limited time to market, Sequential Equivalence Checking technology is receiving a lot of attention in recent years. SEC minimizes the risk involved in making RTL sequential changes late in the development cycle, without changing the functional behavior.
This paper presents the need for Sequential Equivalence Checking method in our design flow and different sequential micro architectural modifications done on the RTL at the end of design cycle to meet high performance design goals related to area, timing and power. Use of Sequential Equivalence Checking methods at different stages in the high performance design and limitations of SEC are also discussed.
Want to know more? Check the below link for the full paper
Sequential Equivalence Techniques for High Performance Design
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