Spare Cells

I have been writing an article on ECO flows.Of course I cannot talk about freeze_silicon ECOs without talking about spare cells.When I was a wee intern sitting through PnR training, spare cells confused me. I thought I had to insert the spares and use them in the same session! So here’s a small note about spare cells.

Spare cells are just that.They are extra cells placed in your layout in anticipation of a future ECO.When I say future, I mean after you taped out and got your silicon back.After silicon tests complete, it might become necessary to have some changes to the design.There might be a bug, or a very easy feature that will make the chip more valuable.This is where you try to use the existing “spare” cells in your design to incorporate the design change.For example, if you need a logic change that requires addition of an AND cell, you can use an existing spare AND to make this change. This way, you are ensuring that the base layer masks need no regeneration. The metal connections have changed, and hence only metal masks are regenerated for the next fabrication.

Inserting Spare Cells

Spare cells need to added while the initial implementation. There are two ways to do this.

  1. The designer adds separate modules with the required cells. You start your PnR with spare cells included, and must make sure that the tool hasn’t optimized them away. There can be more than one such spare modules, and they will be typically named spare* or some such combination. The inputs are tied to power or ground nets, as floating gates shouldn’t be allowed in the layout. The outputs are left unconnected.
  2. Use a command provided by the PnR tool to add the spare cells to the netlist in placement stage. An example using ICCompiler command is given below.
  3. Spare Cell Placement

    You need to give some thought as to where to place your spare cells in layout.They are not timing critical, and if you do not give any constraints, PnR tool will place them all together.However, you do not know which area of the layout will eventually require a connection to the spares.You can have two placement approaches.

    Sprinkled Spares
    Sprinkled Spares
    • Sprinkle the individual spare cells in your layout, so from any point you may have a reasonably close library cell.
    • Group the spare cells in multiple groups and sprinkle/place each group in the layout.
    Grouped Spares
    Grouped Spares
    If the spare cells are included in the netlist, you need to set an attribute spare_cell so that the PnR tool does no optimize these. If you do not set them as spare_cell or set a dont_touch, you will find that after placement all spare cells are gone.

    Given below is an example of spare cell placement as grouped instances. Here it is assumed that the spare cells are instantiated in the netlist as spare_i_1 & spare_i_2.

    And here’s an example of inserting & placing spare cells using ICC. You can group the cells by giving cell names, which I haven’t done below. It is sprinkled individually instead.

    Note that I have used a command set physopt_tie_spare_cells true in the examples above. This ensures that the inputs are tied to TIE cells in the subsequent placement stage, instead of connecting directly to the power or ground lines. If you want to control the number of pins connected to a TIE cell, use the command set_max_fanout 1 libname/TIE* before running the above commands.

29 Comments

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    1. Spare cells are not special cells. The existing cells from the used standard cell library are included as ‘spare’ cells. The only difference is that the input pins are tied to VDD/VSS instead of signals. So the internal structure is the same as any other NAND/NOR/AND/FF in the library.

      Some libraries may have special cells that can be metal programmed into any kind of cell that can be used as spare cells.

      1. Prashant

        Madam please tell me wat are spare cells and y do we use them and at which stage we use them?
        and tell me that what are the checks that we do after floorplanning and placement steps?

  3. renjith

    Could you please give a detailed description including pictures on Tie high and tie low cell. How it is helpful since we are using it to avoid the direct connection of gate of unused pins with VDD and GND…

    1. mm Sini Mukundan

      If you are using Cadence EDI for placement, use the following command

      After placement check the netlist to verify the spares.

  4. Sarath chandra

    Hi mam,
    Whats the difference between Link library and Target library?I have gone through EDA board website and got some clarity regarding this. But I want to know in what way these 2 libraries differ ?

    Thanks in advance

    1. Consider you have the following components in your design
      1. Std cells from library stdA
      2. memory from memA
      3. A hard macro from AnaA
      4. Level shifters from lsA

      In this scenario, your link_library will have the paths to the .db files for all of the above libraries.

      Your target_library will be the .db of stdA, your standard cell library. This is the library the tool will use to synthesize(in case of synthesis) and optimize (in case of P&R).

  5. Sarvang Sanghavi

    Ma’am,
    If suppose after tapeout, i find that my spare cells aren’t of any use than is there any way to remove them ? Because as inputs of spare cells are connected to VDD/VSS , there would be some power drop at input of spare cells so is there any way to remove spare cells after tapeout ?

  6. Navunattha

    Hi
    When I am adding spare cells it spreads everywhere. What if I want to group together all the spare cells(like you explained in 2 placement approaches) at particular coordinates .I am using cadence encounter tools and have used
    createSpareModule and placeSpareModule commands. When I use these commands a spare module is created with no instances in it despite giving TU as 70%. After placing of standard cells all spare cells get scattered away

    1. mm Sini Mukundan

      You will have to group the spare cells and place them using a script.
      An easy way would be to have modules that you can group. Then create a group and region for that module. Write a script to place them.

      1. Navunattha

        Hi
        I grouped all the spare modules using placeSpareModule -area command. When I create a region the spare modules donot get placed in that region. I need to place spare module in shape of + . All module are equidistant to each other. Is there any option to place spare modules with only 1 command

        1. mm Sini Mukundan

          Write a script..
          An example you can edit…

          set sizeX 2000
          set sizeY 2000
          set xstart 0
          set ystart 0

          set xdiv 5
          set ydiv 3

          set xbox [expr $sizeX/$xdiv]
          set ybox [expr $sizeY/$ydiv]

          set count 1
          for {set i $xstart} {$i <= [expr {$sizeX-$xbox}]} {incr i $xbox} { for {set j $ystart} {$j <= [expr {$sizeY-$ybox}]} {incr j $ybox} { puts "createRegion inst$count\_spares $i $j [expr {$i+$xbox}] [expr {$j+$ybox}]" createRegion inst$count\_spares $i $j [expr {$i+$xbox}] [expr {$j+$ybox}] incr count } }

  7. shafi

    Hi
    I am having trouble spreading spares cell coming from netlist in EDI.
    When I am adding the spares using CreateSpareModule it works fine, but when the gate netlist already includes the spare cells EDI places all of them clustered in a corner of the floorplan.
    I tried setPlaceMode -moduleAwareSpare false and specifySpareGate -inst before placeDesign, but it seems EDI do not understand these are spares and needs to be distributed (sprinkled).
    Could you please suggest me what else I can try?

    TIA and Regards

  8. bhaskar

    I included a flop in my group of spare cells and connected clk pin of flop to the main clock. Now I am seeing a huge skew between this pin and another flop driven by the same clock i.e. main clock. How should I address this issue? Should I excluded this spare cell in my cts spec file i.e using excludedpin in cts spec file?

  9. bhaskarg

    madam,
    how do we know that, how much percentage of spare cells are required for a particular design…. or is there any formulae to know spare cells percentage with respect to no.of standered cells in design

    thanks in advance madam

    1. mm Sini Mukundan

      There is an option to connect the clock pins to any of your existing clock. This will help in making the spare flop part of the clock tree.
      You can also chose to connect the clk input to 1’b0. In this case, when the flop is used, you will need to connect it to an appropriate brach of clock tree manually.

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