Standard Delay Format

SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF now has the delay numbers derived from these as well as the cell delays associated with the digital cells. SDF or Standard Delay Format is an IEEE specification. SDF is an ASCII format and can include:

1. Delays: module path, device, interconnect, and port
2. Timing checks: setup, hold, recovery, removal, skew, width, period, and nochange
3. Timing constraints: path, skew, period, sum, and diff
4. Timing environment: intended operating timing environment
5. Incremental and absolute delays
6. Conditional and unconditional module path delays and timing checks
7. Design/instance-specific or type/library-specific data
8. Scaling, environmental, and technology parameters

SDFs can be used at any stage in the design flow for an accurate and tool independent representation of circuit delays. In physical design flow, SDF files are used for postlayout simulation & backannotation. The STA tool typically writes out the SDF. This will have both interconnect and cell delay.After P&R you give the following inputs to the STA tool.

  • Netlist
  • .lib file for cell delays
  • SPEF file for extracted parasitics from the layout
  • SDC file for timing constraints

The .lib only has the cell delays in a table form, and the SPEF file has the interconnect parasitics. SDF file combines these information and gives out a file that has accurate delays for each component in the layout database, for the given constraints. This is used along with the netlist in a simulator to verify that design meets its functional & timing requirements.

Let us now try to understand the format in detail. I will skip the header section, since it is more or less self explanatory. Make sure you look at the (TIMESCALE ) statement to verify you are using the correct timescale though.

An SDF file typically has a section similar to the one below.

The SDF INTERCONNECT construct allows interconnect delays to be specified on a point-to-point basis. This is the most general method of specifying interconnect delay.

The above snippet gives the interconnect delays as calculated by the analysis tool. in1 is a port (a physical pin in layout) and there is a wire connecting to the D pin of register top/test_reg. There are two parentheses next to it,with colon separated values.(0.0029::0.0028) corresponds to the delay values when top/test_reg/D makes a 0->1 transition. Similarly the value in the second parenthesis (0.0029::0.0029) corresponds to when this port makes a 1->0 transition. (A typical SDF may only have two such groups, but SDF file can have upto 12 delay values, which corresponds to when the ports makes the following transitions. 0->1, 1->0, 0->Z, Z->1, 1->Z, Z->0, 0->X, X->1, 1->X, X->0, X->Z, Z->X)

Inside each of the delay group, we can have a triplet of values, separated by colon.In the example, we only have two.This means the minimum & maximum corner values are written out by the tool.(With typical values missing.It is NOT zero.)

Now, let us see how cell delay information is incorporated in SDF file.

Let us take the DELAY statement from the above. There are two IOPATHs defined. The CLK->Q delay and the CLRZ-Q delay of the cell. See that the first parenthesis is empty for CLRZ->Q path delay. This means 0->1 values are not specified and might not even be present in the timing model(.lib).

We also have a TIMINGCHECK section above. Timing check entries specify limits in the way in which a signal can change or two signals can change in relation to each other for reliable circuit operation. EDA analysis tools use this information in different ways:

  1. Simulation tools issue warnings about signal transitions that violate timing checks.
  2. Timing analysis tools identify delay paths that might cause timing check violations and may determine the constraints for those paths.

Take (SETUPHOLD (posedge D) (posedge CLK) (0.5805::0.5805) (-0.1512::-0.1512))

The syntax for SETUPHOLD timingcheck statement is ( SETUPHOLD port_tchk port_tchk rvalue rvalue )

The first port_tchk is (posedge D),and identifies the data port D. Since there is a posedge specification, this value is for posedge transition at D.(posedge CLK) identifies the clock port and identifies posedge as the active transition edge.The first rvale (0.5805::0.5805) gives the SETUP time.The second rvale (-0.1512::-0.1512) gives the hold time.Either can be negative, however their sum must be greater than zero.
The WIDTH entry specifies limits for a minimum pulse width timing check.
(WIDTH (posedge CLK) (0.3692::0.3692)) gives the min & max minimum width required of the clock CLK from its positive edge. We can also have a similar statement for (negedge CLK).

There is another common statement which is COND. The COND construct allows any path delay to be made conditional, that is, its value applies only when the specified condition is true.This allows for state-dependency of path delays where the path appears more than once in the timing model with conditions to identify the circuit state when it applies.Annotator must locate a path delay with a condition matching the one specified and apply the data only to that. Other path delays from the same input port to the same output port but with different conditions in the timing model will not receive the data.

(COND A&&!B (IOPATH S Y (0.7427::0.7427) (0.6942::0.6942)))

The Path delay from S->Y is the given values only when the condition A&&!B is matched. i.e. the example below gives the different delays the MUX has depending on which signal is being selected.

COND statements can be used as part of TIMINGCHECKS as well. You may encounter those in your SDFs.

This just starts you off with understanding the SDF file you use for postlayout simulations, and these are the most common statements you encounter in the file.

Sini Mukundan

Sini Mukundan

Staff Engineer at Texas Instruments
Sini is an expert on physical design flow and related methodologies. Outside work, she is an avid reader and generally loves being lazy.
Sini Mukundan

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  1. vijay

    Thanks a ton, i’d been forever confused b/w sdf and lib and how they integrate into the flow, till now.

    The detailed sdf description completes the understanding. Thanks!

  2. Pratik

    Hi Sini,
    Thanks for your detail explanation about SDF.
    I got doubt in SDF syntax. In my case- SDF generated in ETS tool. and in triplet I see only two values (min::max) as explained. But I see in my SDF min values is higher than max value. Is it possible? and if yes then how?
    And second question I have, is how to generate typical values also?
    Waiting for your reply.

    SDF snippet for reference:
    (INSTANCE RECC_SPLT1_edt_i/RECC_SPLT1_edt_decompressor_i/g1436)
    (IOPATH AN Y (0.02830::0.02830) (0.02630::0.02630))
    (IOPATH B Y (
    0.02060::0.02050) (0.02240::0.02240))

    Thank You,

    1. Please see the .lib values.. Are the rise_transition values for MAX and MIN libraries for this pin different and the MIN library value higher than the MAX?

      To get the typical values, use the option -typ_view

      write_sdf -typ_view NOM_setup test.sdf

  3. manasa

    Assume the timescale is in ps

    (INSTANCE Inst_UART_TX_CTRL/bitTmr_1_rt)
    (PORT ADR1 (231:231:667)(231:231:667))
    (PORT ADR5 ( 0 )( 0 ))
    (IOPATH ADR1 O (45:124:124)(45:124:124))
    (IOPATH ADR5 O (45:124:124)(45:124:124))

    from this SDF snippet, the given delay is only for the component and does not include wire delay ???

    Assuming that the given SDF snippet shows the delay of a component alone is the total delay the largest delay of the two IOPATH i.e. 124ps or the addition of the individual delays of the two IOPATH i.e. (124+124)ps
    (Assuming i’m calculating the worst case delay for the component)

    1. Sini Mukundan

      This doesn’t have INTERCONNECT statement because you have some other model available. Is X_LUT6 a standard cell or a hard macro with a .lib available? Check Inst_UART_TX_CTRL for wire delays.

      (IOPATH ADR1 O (45:124:124)(45:124:124)) –> The path delay from ADR1 to O is 124ps when the transition is 0->1 & 1->0 for worst case.

      1. manasa

        x_lut6 is a component as part of xilinx FPGA board. Specifically the SDF file snippet is from a circuit on a virtex 7 board.

        What I understand from the IOPATH statement is that it gives the delay from the i/p to o/p port (minimum:typical:maximum). Now when a instance has more than one IOPATH statement as in the above case what would be the delay of that instance ??

  4. Rameez Raza

    The article is very helpful in understanding the SDF files.
    I have a doubt related to SDF files , if wea have different sdf files for min,max and typ corners and each file have delay values like this (0.0029::0.0028), so does it mean i am missing typical values.Please clarify

  5. samarshekar

    My work is criticality computation in SSTA. For this i converted circuit into timing graph G(V,E). For all ISCAS 85 bench circuits. I synthesized synopsys DC for all and primetime also.

    Now i need to extract gate and net delays from SDF files for individual nodes for the timing graph. I have to calculate timing quantity for each node. To calculate i need to extract delays from SDF file and Perform timing calculation at each node.
    How to extract delays from sdf …do we have any script for that or we need to do back annotation……hel me…plz

  6. Samarshekar

    How to extract gate delays and net delays from SDF files. Do we have any scripts for that. I need to extract these delays values to perform statistical timing analysis.

    Fats and accurate SSTA ieee paper

  7. kvin

    .After P&R you give the following inputs to the STA tool.
    ◾.lib file for cell delays
    ◾ SPEF file for extracted parasitics from the layout
    ◾ SDC file for timing constraints
    I am confused of SDC file needed for generating sdf, why we need the timing constraints ? And which constraint only in the SDC file ? which should not be inside SDC file ? ex set_ideal_network etc ?

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