System Verilog: Random Number System Functions

System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers.

The $random verilog system function has only one random number generator shared between all threads, but each thread in simulation has its own random number generator for $urandom and $urandom_range. Separate random number generators for each thread helps to improve random stability

The $urandom() system function provides a mechanism for generating pseudo-random numbers. The function returns a new unsigned 32-bit random number each time it is called.

The seed is an optional argument that determines the sequence of random numbers generated.
This generates 32 bit unsigned number, but 2 bits, 4 bits etc. random numbers can be generated as shown below.

The $urandom_range() function returns an unsigned 32 integer within a specified range. Range would be specified using max and min values as shown below

In the below code addr1 range is from 32’hFFFF_FF00 to 32’hFFFF_FFFE. So it generated following values in 5 iterations.

The srandom() method allows manually seeding the RNG of objects or threads.

The srandom() method initializes an object’s RNG using the value of the given seed.

In the below code 5 iterations are done without setting a seed using $srandom(). So different random numbers are generated. But once we set srandom(1), RNG will generate same random numbers. This will change once we change the seed.

One Comment


    i executed the program using $srandom(1). but i didn’t get same random numbers using $srandom. will you check once the given code is proper. i am using questasim simulation tool

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