Standard Delay Format
SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF now has the delay numbers derived from these as well as the cell …
Tag: timing
set_clock_uncertainty
There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means. The SDC manual states that set_clock_uncertainty Specifies the uncertainty or skew characteristics of a single clock or between two …
set_timing_derate
set_timing_derate set_timing_derate is a command that lets you constraint the timing a bit more. The idea and application is simple enough, but you might get confused with all the talk about process variation and OCV …
SPEF Files Explained
Standard Parasitic Exchange Format(SPEF) is an IEEE format for specifying chip parasitics. The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System . Latest …
Reading ICC Timing Reports
At any stage of the design you will be reporting timing. You can use your PnR tool to report the timing after placement, after CTS and various stages of routing and optimization. Even though the …
Synopsys Design Constraints
Timing closure is the big whale for most P&R designers. You get it done, and then you can wash your hands off all those annoying designers and get to work cleaning up and beautifying your …