Verilog: Timescales
As we are aware, compiler directive ``timescale` in Verilog is a tricky topic and have many discussion around it. Timescale specifies the time unit and time precision of a module… Read more »
Tag: Verilog
Verilog: Timing Controls
Timing Controls Timing control statements are required in simulation to advance time. The time at which procedural statements will get executed shall be specified using timing controls. Delay based, event… Read more »
Verilog: Continuous & Procedural Assignments
Continuous Assignment Continuous assignment is used to drive a value on to a net in dataflow modeling. The net can be a vector or scalar, indexed part select, constant bit… Read more »
Verilog: Task & Function
Task and Function are used to break up large procedures into smaller ones which helps to make life easier for developing and maintaining Verilog code. In this way, common procedures… Read more »
Verilog: Control Statements
By using control statements, you can decide the order in which statements are executed. Conditional statements If-else case Loops forever repeat while for if-else Conditional statements are used to decide… Read more »
Verilog: Operators
Operators are single-, double-, or triple-character sequences and are used in expressions.Following operators are available in Verilog HDL. Please note that not all operators are synthesizable. {} {{}} Concatenation +… Read more »