To discuss the svt, hvt and lvt cells used for power aware designing, we need to first iterate our understanding of threshold voltage.
Let’s consider the NMOS in the above figure. Here, source and substrate (backgate) are connected together to VSS. Substrate is P-type, drain and source are N-type. Now, apply a positive voltage to the with respect to the source/substrate. As the gate is positively biased with respect to substrate, there will be an accumulation of electrons under the gate area, effectively making that region an b-biased area within the substrate. At some Vgs(Gate-to-Source voltage), there forms
a n-type channel between the drain and source unders the gate area. The threshold voltage by definition is the gate to source bias required to just form this channel.For any gate-to-source voltage less than this threshold voltage, no conducting channel forms.
A number of factors affect the threshold voltage:
1. Substrate doping
Threshold voltage increases with substrate doping. With channel formation, the p-type substrate will have to invert itself to n-type near the gate. As the doping increases, a higher bias is required to move the majority carriers away from the channel region. This can be circumvented by adjusting the doping just beneath the gate area.
2. Gate doping
Poly doping increases the conductivity of the poly silicon gate. Due to poly depletion, this aids in the formation of the channel thereby reducing the threshold voltage as doping increases.
3. Channel length
As the channel lengths lower, threshold voltage reduces. This manifests as the short channel effect in MOSFETs with longer channel when drain voltage is kept high. But when the channel length is short, this lowering of threshold voltage can be seen without drain voltage as well.
4. Gate Oxide
Thicker gate oxide increases threshold voltage of the device, whereas thinner dielectric reduces the threshold voltage.
1. Body Effect