Verilog: Control Statements

By using control statements, you can decide the order in which statements are executed.


if-else
Conditional statements are used to decide which statement in a group of choices is executed. If a condition is evaluated to true, one statement is executed. If the condition evaluated to false, the else part of the code is executed.

Testbench

case statement
case statement is a multiway decision statement. i.e. a number of values may be the evaluated value of the condition. You can implement case with if-else if as well.

Use the same testbench as above.

forever
forever continuously executes a statement. Most common example would be a simple clock generator.


repeat
repeat repeats the statement a fixed number of time.

while loop
The while loop repeats a statement until the condition becomes false.

for loop
for loop has three parts separated by semicolon. First is an initialization statement, which initializes the variable that will control the loop. The second part is the condition in which the loop will be entered. Third part modifies the control variable after every loop entry.

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