Verilog: Task & Function

Task and Function are used to break up large procedures into smaller ones which helps to make life easier for developing and maintaining Verilog code. In this way, common procedures need to be written only once and can execute from different places. Both task and function are called from always or initial block and contain only behavioural statements.

Definition of task and function must be in a module. The highlighting difference between task and function is that, only task can handle event, delay or timing control statements and function executes in zero simulation time. There are some more differences, which we will be discussed in this sesssion.

Task

Task is declared using task & endtask keyword. Task must be used if delay, event or timing control constructs are required in the procedure. It may have zero or more than input,output or inout argument. As it executes in non-zero simulation time, it can enable other task and functions. It does not return value like function instead it can pass multiple value through output or inout arguments.

Automatic task

If a task is called concurrently from different places in the code these task calls will operate on the same task variables. This may leads to incorrect result. To avoid this problem a keyword automatic is added to make the task reentrant.

Function

Functions are declared using function & endfuncion keywords. Function can be used if there is no requirement for specifying delays, timing control constructs or events. There is at least one input argument is needed to use function. Function will return a single value and it usually uses for calculations. Also note that it cannot have output or inout arguments. As it cannot handle timing control statement, delays etc and executes in 0 simulation time, it can only enable another function and not task.

Function Example

Below example shows how to calculate parity using function. A simple code, but always used in the designs.

Automatic (Recursive) Functions

If normal functions are called recursively, the results are non-deterministic because both calls operate on the same variable space. But by using automatic keyword, all function declarations are allocated dynamically for each call and operate on independent variable space. Following is a well known example for automatic function.

Constant Function

Constant function can be used to instead of constants. In the below example it calculates AWIDTH by using constant function.

Signed Function

If signed operation needs to performed on return value, then that function must be defined using signed keyword.

Task & Function Differences at a glance

Task Function
May execute on non-zero simulation time Executes on zero simulation time
May have delay, event or timing control constructs Not possible as it executes on zero simulation time
Cannot return a value Always return a single value
Pass values (can be multiple) through output or inout arguments Cannot have output or inout arguments
Can enable other functions and tasks Can enable other functions and not task
Can have input, output or inout Must have atleast one input. Cannot have output or inout
Sini Balakrishnan

Sini Balakrishnan

Staff Engineer at Intel
Sini has spent more than a dozen years in the semiconductor industry, focusing mostly on verification. She is an expert on Formal Verification and has written international papers and articles on related topics.
Sini Balakrishnan

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13 Comments

  1. Bnote

    I’m not sure but I think the result is following for the task example.
    0 –>muxin = 0111, msel = 01, mout = 1
    10 –>muxin = 0111, msel = 10, mout = 1
    20 –>muxin = 0110, msel = 00, mout = 0
    Instead the result is written in your task box
    Simulation result:
    ncsim> run
    0 –>muxin = 0111, msel = 01, mout = 1
    10 –>muxin = 0111, msel = 10, mout = 1
    20 –>muxin = 0111, msel = 00, mout = 1
    Simulation complete via $finish(1) at time 120 NS + 0
    ./mux.v:74 #100 $finish;

    Would you tell me the right answer?

    1. Yes. This is the right answer. Thanks for pointing out.
      ncsim> run
      0 –>muxin = 0111, msel = 01, mout = 1
      10 –>muxin = 0111, msel = 10, mout = 1
      20 –>muxin = 0110, msel = 00, mout = 0
      Simulation complete via $finish(1) at time 120 NS + 0

      1. Ameera

        hi,
        please can you put an example of task calling a task?
        and I have a question if you please, let us say that task#1 calls task#2, does task#2 executes in the same clock cycle of task#1 or it will be the next cycle ??
        actually I want to implement two tasks say X and Y, task X should start in the first clock cycle then task Y will be repeated n times, each time in a different clock cycle … how this could be implemented ?
        Thanks in advance. 🙂

        1. Please find below example for task calling another task.

          This depends on how you invoke the tasks in your code. You can model it as per your requirement. You can model to call it at the same time or in the different clock cycles or after some specific time period etc.

          Here your requirement is to invoke the task1 in the first clock cycle and task2 in the upcoming cycles. This can be implemented in the following method.

          //////////////////////////////////
          module task_check(clk);

          input wire clk;
          integer n;

          initial begin
          task1;
          end

          task task1;
          begin
          $display($time,” —-> Am in task 1\n”);
          for (n=0; n < 15; n=n+1) begin @(posedge clk) task2; end end endtask task task2; $display($time," =====> Am in TASK2 \n”);
          endtask
          endmodule

          ////////////////////////////////////
          module test(clk);
          output reg clk = 1’b0;
          task_check tt(clk);
          always #5 clk = ~clk;

          initial begin
          #200 $finish;
          end
          endmodule
          ////////////////////////////////////
          ncsim> run
          0 —-> Am in task 1

          5 =====> Am in TASK2

          15 =====> Am in TASK2

          25 =====> Am in TASK2

          35 =====> Am in TASK2

          45 =====> Am in TASK2

          55 =====> Am in TASK2

          65 =====> Am in TASK2

          75 =====> Am in TASK2

          85 =====> Am in TASK2

          95 =====> Am in TASK2

          105 =====> Am in TASK2

          115 =====> Am in TASK2

          125 =====> Am in TASK2

          135 =====> Am in TASK2

          145 =====> Am in TASK2

          /////////////////////////////////////////////

          Here task1 will get called in the first posdge of clk (simulation time 5) and task2 will get called 15 times in the simulation time 15,25,35 etc.

          Hope this helps.

          1. Ameera

            Thanks very much Sini Balakrishnan, it was very helpful.
            but I don’t want task X to run at CLK #1 and stops, actually what I want is something like a thread;
            Suppose each thread starts with task X in its first CLK then task y in the upcoming cycles.

            I want to run multiple threads with a one CLK delay between one thread and the next.

            Thanks for helping, I appreciate it.

  2. Garima

    Hello,
    I am writing a memory in verilog using read and write task.
    I am getting this error : Hierarchical name component lookup failed at ‘WRITE’.
    I am not understanding why it is coming.Can you please tell me..


    module memory(data_out,data_in,address,we,clk);
    input clk,we;
    input [1:0]address;
    input [3:0]data_in;
    output [3:0]data_out;
    reg [3:0]data_out;
    reg [1:0]mem[3:0];
    always @(posedge clk or we)
    begin
    $display("I am in main module");
    if(we)
    mem[address]<= data_in ;
    else
    data_out <= mem[address];
    end

    task WRITE;
    input [3:0]data_in;
    input [1:0]address;
    output [3:0]data_out;
    reg [3:0]data_out;
    input clk,we;
    begin
    $display("I AM in WRITE TASK");
    @(posedge clk);
    we=1'b1;
    end
    endtask

    task automatic READ;
    output [3:0]data_out;
    reg [3:0]data_out;
    reg [1:0]mem[3:0];
    input clk,we;
    input [1:0]address;
    begin
    $display("I AM IN READ TASK");
    @(posedge clk);
    we=0;
    end
    endtask
    endmodule

    module test;
    reg clk,we;
    reg [1:0]address;
    reg [3:0]data_in;
    wire [3:0]data_out;

    memory mem1(data_in,data_out,clk,we,address);

    //writing into memory
    initial
    begin
    clk=1'b0;
    we=1'b0;
    address = 2'b0;
    data_in = 4'b0;
    end
    always #10 clk =~clk;

    initial
    begin
    $dumpfile ("mem.dump");
    $dumpvars(0,test);
    #200 $finish;
    end

    initial
    begin
    WRITE(0,1);
    WRITE(1,2);
    READ(0,1);
    end
    initial
    //Reading data from location "2"
    $monitor("Time",$time,"\t" ,"data_in=%b data_out=%b address=%b ",data_in,data_out,address);
    endmodule

  3. chan

    Hi Sini,
    Your work is quite impressive. If possible pls clear my doubt. My o/p value always coming out as “X”. could you pls identify the source of error?
    A few points add to validate my code. A single task called by two diff calls with different values passed by.
    module vga_model(hsync,vsync);

    output hsync,vsync;
    reg vsync,hsync;

    parameter hfp=5,hbp=8,hpw=6,hdt=6;
    parameter vfp=10,vbp=7,vpw=4,vdt=5;
    reg clk;
    always #5 clk=!clk;

    initial
    begin
    clk = 1’b0;

    $monitor($time,”MODEL:: hsync=%b vsync=%b”,hsync,vsync);
    fork
    vga_sig_gen(vdt,vfp,vbp,vpw,vsync);
    vga_sig_gen(hdt,hfp,hbp,hpw,hsync);
    join

    end

    task automatic vga_sig_gen;
    input [31:0] dt;
    input [31:0] fp;
    input [31:0] bp;
    input [31:0] pw;
    output sync;
    reg sync;

    begin
    $display($time,”%h %h %h %h %b”,dt,fp,bp,pw,out);
    // display time cycles
    repeat(dt)
    begin @(posedge clk);sync=1’b1;$display($time,”Am in display time cycles =%b”,sync); end
    repeat(fp)
    begin @(posedge clk);sync=1’b1;$display($time,”Am in Front porch cycles =%b”,sync); end
    repeat(pw)
    begin @(posedge clk);sync=1’b0;$display($time,”Am in back porch cycles =%b”,sync); end
    repeat(bp)
    begin @(posedge clk);sync = 1’b1;$display($time,”Am in pulse width cycles =%b”,sync); end
    end//task begin
    endtask
    endmodule

    module tb_vga;
    wire hsyn,vsyn;
    initial
    begin
    $monitor(“TB : hsync=%b vsync=%b”,hsyn,vsyn);
    end
    vga_model ref_inst(.hsync(hsyn),.vsync(vsyn));
    endmodule

    1. Hi,
      I am not sure about the logic which you are trying to implement. But with slight changes in the code, I could see TB gives values for hsync and vsync.
      ////////////////////////////////////////////////////
      module vga_model(hsync,vsync);

      output hsync,vsync;
      reg vsync,hsync;

      parameter hfp=5,hbp=8,hpw=6,hdt=6;
      parameter vfp=10,vbp=7,vpw=4,vdt=5;
      reg clk;
      always #5 clk=!clk;

      initial
      begin
      clk = 1’b0;
      $monitor($time,”MODEL:: hsync=%b vsync=%b”,hsync,vsync);
      fork
      vga_sig_gen(vdt,vfp,vbp,vpw,vsync);
      vga_sig_gen(hdt,hfp,hbp,hpw,hsync);
      join
      end

      task automatic vga_sig_gen;
      input [31:0] dt;
      input [31:0] fp;
      input [31:0] bp;
      input [31:0] pw;
      output sync;
      reg sync;

      begin
      $display(“called task —————- “);
      $display($time,”%h %h %h %h”,dt,fp,bp,pw);
      // display time cycles
      repeat(dt)
      begin @(posedge clk);sync=1’b1;$display($time,” Am in display time cycles =%b”,sync); end
      repeat(fp)
      begin @(posedge clk);sync=1’b1;$display($time,” Am in Front porch cycles =%b”,sync); end
      repeat(pw)
      begin @(posedge clk);sync=1’b0;$display($time,” Am in back porch cycles =%b”,sync); end
      repeat(bp)
      begin @(posedge clk);sync = 1’b1;$display($time,” Am in pulse width cycles =%b”,sync); end
      end//task begin
      endtask
      endmodule

      ////////////////////////////////////////////////////

      module tb_vga;
      wire hsyn,vsyn;

      vga_model ref_inst(.hsync(hsyn),.vsync(vsyn));

      initial
      begin
      $monitor(“TB : hsync=%b vsync=%b”,hsyn,vsyn);
      #500 $finish;
      end

      endmodule
      ////////////////////////////////////////////////////
      245 Am in pulse width cycles =1
      TB : hsync=1 vsync=x
      255 Am in pulse width cycles =1
      TB : hsync=1 vsync=1

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