module tb;
reg [3:0] a ;

wire resultAND, resultNAND, resultOR, resultNOR, resultXOR,resultXNOR  ; 

dut dut_inst ( resultAND, resultNAND, resultOR, resultNOR, resultXOR,resultXNOR, a ) ;

initial
begin
   a = 4'b1010 ;
   #10 ;
   $display("resultAND : %b, resultNAND: %b ,resultOR: %b , resultNOR: %b , resultXOR: %b ,resultXNOR: %b ", resultAND, resultNAND, resultOR, resultNOR, resultXOR,resultXNOR );

end
endmodule