Recovery and Removal Checks
Recovery and removal analysis are done on asynchronous signals like resets. These specify the requirement of these signals with respect to clock.Recovery Time is the minimum required time to the… Read more »
Author Archives: Sini Mukundan
Verilog: Control Statements
By using control statements, you can decide the order in which statements are executed. Conditional statements If-else case Loops forever repeat while for if-else Conditional statements are used to decide… Read more »
Verilog: Operators
Operators are single-, double-, or triple-character sequences and are used in expressions.Following operators are available in Verilog HDL. Please note that not all operators are synthesizable. {} {{}} Concatenation +… Read more »
Integrated Clock Gating Cell
Clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal.Clock gating functionally requires only an AND or OR… Read more »
Standard Delay Format
SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF now has the delay numbers derived from these… Read more »
Multi Cycle Paths
By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that some data is captured only after a specified… Read more »
STA – Setup and Hold Time Analysis
It is easy to get confused with the definitions of setup and hold violations. We are used to the definitions of setup and hold times for a single flipflop. The… Read more »
Clock Jitter
In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock jitter is a characteristic of the clock source… Read more »
Insertion Delay & set_clock_latency
Clock latency refers to the delay that is assumed to exist between the clock source and the flip-flop clock pin. This is typically used before layout, when clock is ideal…. Read more »
set_clock_uncertainty
There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means. The SDC manual states that `set_clock_uncertainty Specifies the uncertainty or skew characteristics of a… Read more »