Integrated Clock Gating Cell
Clock gating is a common technique for reducing clock power by shutting off the clock to modules by a clock enable signal.Clock gating functionally requires only an AND or OR… Read more »
Category: Back End
Standard Delay Format
SDF file is how you represent your circuit delays. We have earlier seen SPEF format which is the circuit’s RC representation. SDF now has the delay numbers derived from these… Read more »
Multi Cycle Paths
By default, we expect every timing path to meet setup time in a single clock cycle. However, we can also specify that some data is captured only after a specified… Read more »
STA – Setup and Hold Time Analysis
It is easy to get confused with the definitions of setup and hold violations. We are used to the definitions of setup and hold times for a single flipflop. The… Read more »
Clock Jitter
In the article Clock Uncertainty I mentioned that the command set_clock_uncertainty is used to account for among other things, clock jitter. Clock jitter is a characteristic of the clock source… Read more »
Insertion Delay & set_clock_latency
Clock latency refers to the delay that is assumed to exist between the clock source and the flip-flop clock pin. This is typically used before layout, when clock is ideal…. Read more »
set_clock_uncertainty
There is the SDC command “set_clock_uncertainty” and there is the question of what clock uncertainty means. The SDC manual states that `set_clock_uncertainty Specifies the uncertainty or skew characteristics of a… Read more »
Physical Design Flow V: Physical Verification
I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis IV. Routing After routing, your layout is complete. Now a number of checks are performed to verify that the drawn… Read more »
Physical Design Flow IV:Routing
I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis After CTS, the routing process determines the precise paths for interconnections. This includes the standard cell and macro pins, the… Read more »
Physical Design Flow III:Clock Tree Synthesis
I. NetlistIn & Floorplan II. Placement For synchronized designs, data transfer between functional elements are synchronized by clock signals. In a top level digital design, you will have one more… Read more »