ESD II : ESD Protection Device
The principle of ESD protection devices is based on clamping the input voltage to a level that is safe for the IC to handle. In the circuitry given using Zener… Read more »
Category: Physical Design
Multicycle paths between different clock domains
We have seen set_multicycle_path constraint for timing path within a single clock domain. Now let’s explore multicycle paths with two synchronous clock domains of different frequencies. The SDC command `set_multicycle_path`… Read more »
Peak and Average Power
If you were to measure the power dissipated by a chip over a time period, the dissipated power vary at each instant of time. Peak power refers to the maximum… Read more »
Multi-VT Cells
At lower technology nodes, leakage power is proving to be a major component of power with the lowered supply and threshold voltage. One method to better balance power and timing… Read more »
Power Dissipation: Leakage Power
Part 1: Sources of Leakage Reduction of power consumption is a requirement for semiconductor devices. First let us list the sources of power to understand how to go about reducing… Read more »
Body Effect
1. Threshold Voltage Body effect refers to the change in the threshold voltage of the device when there is a difference between substrate(body) and source voltages. Body bias is usually… Read more »
Threshold Voltage
To discuss the svt, hvt and lvt cells used for power aware designing, we need to first iterate our understanding of threshold voltage. Let’s consider the NMOS in the above… Read more »
Clock Groups : set_clock_groups
Back when I gave an introduction to SDC, I brushed upon `set_false_path` statements between clocks. However, now there is a more efficient way of specifying the the clock exceptions in… Read more »
Two Stage Synchonizers
When an asynchronous signal, or a signal from a block clocked by a different clock is received by a synchronous circuit, it is imperative that it is reliably sampled by… Read more »
Common Path & Clock Reconvergence Pessimism Removal
Many a time your chip is overdesigned due to undue pessimism in timing calculations. Pessimism in timing analysis makes it difficult for designs to close timing and it is imperative… Read more »