Physical Design Flow IV:Routing
I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis After CTS, the routing process determines the precise paths for interconnections. This includes the standard cell and macro pins, the… Read more »
Category: Physical Design
Physical Design Flow III:Clock Tree Synthesis
I. NetlistIn & Floorplan II. Placement For synchronized designs, data transfer between functional elements are synchronized by clock signals. In a top level digital design, you will have one more… Read more »
Physical Design Flow II:Placement
I. NetlistIn & Floorplan After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to… Read more »
Physical Design Flow I : NetlistIn & Floorplanning
This is going to be a series of step-by-step explanation of physical design flow for the novice. I am going to list out the stages from Netlist-GDS in this session…. Read more »
set_timing_derate
set_timing_derate set_timing_derate is a command that lets you constraint the timing. Forget the process variation and OCV for now and let’s uncomplicate and first see how the command works. Timing… Read more »
ECO
Engineering Change Order or ECO is how you incorporate last minute changes in your design. ECO saves money and time and is prevalent in the industry. When I talk ECO,… Read more »
Spare Cells
I have been writing an article on ECO flows.Of course I cannot talk about freeze_silicon ECOs without talking about spare cells.When I was a wee intern sitting through PnR training,… Read more »
SPEF Files Explained
Standard Parasitic Exchange Format(SPEF) is an IEEE format for specifying chip parasitics. The specification for SPEF is a part of standard 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and… Read more »
ICCompiler MCMM Flow – create_scenario
The PnR tools now have concurrent multi-corner and multimode analysis and optimization capabilities. In ICCompiler, we create `scenarios` to specify the different corners and modes the design should operate on…. Read more »
Reading ICC Timing Reports
At any stage of the design you will be reporting timing. You can use your PnR tool to report the timing after placement, after CTS and various stages of routing… Read more »