As the design complexity increases, the use of traditional verification methodology becomes minimal for verifying hardware designs. Directed Tests were used quite long back. Later, Coverage Driven Verification methodology (CDV)… Read more »
Abstract: Quite often in semiconductor industry, when a product is nearing its launch date, most of us have had the déjà-vu situation of performance to time-to-market trade-offs; especially in high-performance… Read more »
Formal verification is a technique used in different stages in ASIC project life cycle like front end verification, Logic Synthesis, Post Routing Checks and also for ECOs. But when you… Read more »
