ASIC Physical Design Flow
In the VLSI design cycle, after the circuit representation is complete, we go to “physical design”. This is the stage where the circuit description is transformed into a physical layout,… Read more »
Category: General
TCL Training Series – Passing an array as procedure argument
A TCL array is an associative array. i.e. there is an (un-ordered) key-value pair in a TCL array. A simple list of elements as in a perl array or a… Read more »
TCL Training Series – upvar
We have seen the command “uplevel” and how to use it earlier. Now, let’s look into a related command upvar. Syntax The TCL language reference manual gives the following description… Read more »
TCL Training Series – uplevel
uplevel is a built-in tcl command that evaluates a script in a different level. Syntax uplevel ?level? arg ?arg …? level here can be number or a # followed by… Read more »
CMOS Latchup
Latch-Up is a condition where a low impedance path is created between a supply pin and ground. To understand latch up we need to understand the various parasitic components in… Read more »
System Verilog: Random Number System Functions
System Verilog provides system functions – $urandom(),$urandom_range() and $srandom() for generating random numbers. The $random verilog system function has only one random number generator shared between all threads, but each… Read more »
System Verilog : Rand & Randc
There are two type-modifier keywords available in system Verilog to declare class variable as random. Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed… Read more »
Noise Margins
Noise margin is the amount of noise a circuit can withstand without compromising its operation. These values are defined so that optimization and analysis can ensure that the spurious signals… Read more »
System Verilog : Fork Join
The fork-join construct enables the creation of concurrent processes from each of its parallel blocks. All the blocks get the same start time and the finish time is controlled by… Read more »
SV Constraint random value generation : Introduction
System Verilog supports three different approaches in verification as follows. 1. Directed Testing 2. Random Testing 3. Directed Random/Constrained Random Testing Directed testing is the traditional verification approach. In this… Read more »