Many a time your chip is overdesigned due to undue pessimism in timing calculations. Pessimism in timing analysis makes it difficult for designs to close timing and it is imperative that analysis is not overly pessimistic. There is a clock path related pessimism observed in timing calculated in on-chip-variation mode, and EDA tools have the capability to automatically remove the pessimism while analysis.
Common Path Pessimism Removal (CPPR)
A timing path consists of launch and capture paths. The launch path has further components – the launch clock path and the data path.
In the above circuit snippet, the launch path is c1->c2->c3 -> CP-to-Q of FF1 -> c5 -> FF2/D
The capture path is c1->c2->c4->FF2/CP
Late and early derates are set for cells and nets while doing timing analysis in on-chip-variation mode. For setup analysis, STA tool does late check for launch clock path and the data path, and early check for the capture clock path. However, part of both capture and launch clock paths are same, till node n1. In the image given, numbers in red denote the max delays(late delay numbers) and numbers in green are min delays(early delay numbers). Let us assume the net delays are included in the numbers.
For setup analysis, the launch clock path delay is:
`1ns+1ns+1ns+ = 3ns`
The capture clock path delay is
`0.8ns+0.8ns+0.8ns = 2.4ns`
However, part of the clock paths is common, till node n1. It is not realistic that these have two different delays for the same analysis. Using the late and early timing numbers for the common path creates unwanted pessimism in timing analysis leading to difficulties in timing closure or overdesign. Hence removal of this pessimism is necessary.
For the example noted above we can see a “CPPR adjustment” of 0.4, i.e. the skew between the clock paths will be 0.2ns, instead of 0.6ns.
`+ CPPR Adjustment 0.4`
Different PD and STA tools have various attributes to selectively enable clock path pessimism removal.
Clock Reconvergence Pessimism
In some case clocks reconverge after taking different paths. In the circuit given below, the clock splits into two different combinational logic before converging through mux m1.
The worst case analysis will have the launch clock path through c3->c4->m1 whereas the capture clock path through c1->m1->c5. This is a possible scenario since the launch and capture are with respect to different clock edges and the mux select could change. In that case, only common path pessimism should be removed. i.e the common elements in the clock paths shouldn’t have different timing numbers. However, if this is not a possibility by design, reconvergence pessimism should be also removed so as to avoid the over design. In hold check, since the timing check is at the same clock edge, this pessimism should always be removed in the analysis.
The clock convergent point in m1/Y.
Launch clock till convergence:
`1ns+1ns+1ns = 3ns`
Capture clock till m1/Y:
`0.8ns+0.8ns = 1.6ns`
Clock reconvergence pessimism: 1.4ns
difference b/w set_load and set_max cap
When you described CRPR, how did you come up with 1.4ns as clock reconvergence pessimism?
Aren’t both the paths exclusive of each other. Then how does it matter if the delays are different on these two paths.
The sta tools tend to take worse case scenarios. CRPR fixes that.
You are considering CRPR while analyzing setup. However, is it not true that as the timing is analyzed on 2 different edges you cannot assume that the circuit will behave in the exact same manner? So, canceling the entire common path delay may not be correct because there will be voltage fluctuations between 2 different time periods. Do you know how does STA tool take that into account?