Creating .lib file from verilog

Creating a dummy .lib file is something every physical design engineer has done now and then. If you have a verilog model of the block available, your task gets easier. The following script automates .lib generation from your verilog netlist. Use this as a dummy .lib to get your design flow going or use it as a template for your analog blocks for modifying the values.

Customize, edit and use. The script creates a simple Data Structre. So any modification can be done pretty easily. The script parses the verilog for the module name specified, and collects the ports & directions. In the .lib file written out, a default capacitance and transition value is specified. This is a good starting point for your blocks.

Usage: create_lib <verilog_netlist> <module_name> [transition_value] [capacitance_value]

20 comments on “Creating .lib file from verilog

  1. Nizam

    Hi Sini,
    script is very good.
    I tried to run by using simple Verilog netlist.
    The usage is not clean for.
    If I run ur usage I am getting create_lib is not recognized as internal or external command.
    Please help to get a dummy .lib for my simple Verilog netlist by providing execution/usage

    1. Sini Mukundan Post author


      Type ” which perl” from your terminal. In this script there is #!/usr/bin/perl at line1. Replace the /usr/bin/perl part with your “which perl” result. Then you should be able to run it without perl command.

  2. vinay kumar

    The script is very useful but i am getting an error
    “: bus_7_0 : input
    : bus_7_0 : input

    What changes need to be made in script to avoid this

  3. Sarath

    Hi Sini,
    Could you please give me a perl script to reduce maxcap violations.
    If possible just give me an overview of maxcap violations and methods to reduce them.

  4. Sandeep

    Hi madam,
    I have a doubt in timing, if u have time just look it and give me some suggestion…
    1.How can “setup and hold” violations happen in the same path…? What are the reasons for it and how can that issue be solved?

  5. Yuvi

    setup & hold are mutually exclusive, but they can occur for same endpoints in different corners due to variation exhibiting by std cells.

  6. Kunal

    Hi Sini,
    My name is Kunal Ghosh. I run online VLSI courses on

    Nice script to start with.

    I wanted to ask, if its ok to modify and use your above dummy lib generation script in one of my courses. I will acknowledge you in my course work for the same

    Hoping to collaboratively work with you


    1. Sini Mukundan Post author

      Hi Kunal,

      We are licensed under CC-BY-NC. While your usage might be commercial, please consider this mail as approval to use with attribution.


  7. jayant saxena

    i have used ur scripts to generate .lib from verilog ,its working fine but now i want to modify this script such that my .lib should also contain information of power pin eg
    pg_type : primary_ground;
    voltage_name : gnd;
    pg_type : internal_ground;
    voltage_name : gnds;
    pg_type : primary_power;
    voltage_name : vdd;
    pg_type : internal_power;
    voltage_name : vdds;
    this type of information i want to add alonfg with cell name how to do this can u tell me ?

    1. Sini Mukundan Post author

      You need a pattern.
      Do you have supply1/supply0 statements for you power pins in the verilog files? If so, use that for another level of parsing.

  8. Apurv

    Its great blog…
    i have one questions, can u tell me how we can extract net length from def file without loading it in tool using any perl or tcl??

    like m1 layer net length is this
    m2 layer net length is wise

  9. Mahendra Reddy

    Hi Sini,

    This script does not work if the input|output|inout signals are defined in multiple lines in the verilog.

    For example:
    input a,b,

    Script generates pin attributes only for “a” & “b” pins in .lib, but not for “c”.

    Please look into the same.


  10. nageswar

    Hi Sini,

    as part of my project work,I have standard cells .libs info, using this info I need generate Verilog code with dummy connections and not required functionally . It is like your above script that has to generate dummy verilog or RTL code based on .libs cell info to just run through synthesis flows.Can you please help me to provide script may help me to do this if you have it? i have seen above your script does reverse way.





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