Clock latency refers to the delay that is assumed to exist between the clock source and the flip-flop clock pin. This is typically used before layout, when clock is ideal. It is not the actual delay, but the delay specified by the user, to account for the clock network delay after implementation.
There are two terms associated with latency—Clock source latency is the time the clock signal takes to be propagated from its ideal waveform origin point to the clock definition point in the design. Network latency is the time the clock signal takes to be propagated from the clock definition point in the design to the clock pin of the sequential device.—The timing analyzer uses this information to determine clock arrival times in the absence of propagated clocking.
Once CTS is complete, the actual delay values to the clock sync points can be calculated. These are typically called insertion delays at this point. (Though some literature does use latency when defining skew as the “difference in best and worst latency”). In short, latency is the value we give the tool before CTS, and insertion delay is the actual value after CTS.
The command `set_clock_latency` Specifies explicitly the source latency or network latency of a clock. This command is typically used before layout, when propagated clocking cannot be used.
set_clock_latency 3.4 [get_clocks SCLK] `
In the timing report, the clock path will have the latency added as the clock network delay. The clock is ideal at this stage, but with a delay.
clock SCLK (rise edge) 200.00 200.00 clock network delay (ideal) 3.40 203.40
After CTS, use the command `set_propagated_clock` to use the real insertion delay values.
Also see set_clock_uncertainty command.
It helps if you mention the delay is shown added to the required or arrival section of the timing reports.
I have set a clock uncertainty for Hold time, I have also used the set_fix_hold to fix hold violations(I am assuming it adds buffers in the data path). After this command why does hold time violations still occur?
After setting ‘set_hold_fix’, you need to run some optimization command, like route_opt.
Or you are doing it at CTS stage, clock_opt
In dc_shell -topographical I cannot find the route_opt or clock_opt.
I assumed you were doing P&R in ICC.I am not that familiar with dc flow.
why we should try to keep the insertion delay minimum as possible if skew remains almost constant?
ocv impact will be there for long clock tree,but it can have crpr leverage if shared by common path as well right.Is there any other reason other than this to keep insertion delay low. ?
Thanks in advance
Ma’am can you help me with the procedures required to calculate existing clock skew of a circuit in Cadence tool? Actually I have to calculate skew generated due to NBTI.
report_clock_timing -type skew
If suppose for a block clock insertion delay number is kept high will it effect the skew number & how