Popular EDA Tools
Here is a list of major EDA tools for various stages of (mostly digital) design flow. These are tools considered stable and suitable for sign-off by the industry. This is… Read more »
Formal Verification – An Overview
Formal verification is a technique used in different stages in ASIC project life cycle like front end verification, Logic Synthesis, Post Routing Checks and also for ECOs. But when you… Read more »
Synopsys Design Constraints
Timing closure is the big whale for most P&R designers. You get it done, and then you can wash your hands off all those annoying designers and get to work… Read more »